THC63LVDM83R Datasheet, PDF (8/12 Pages) THine Electronics, Inc. – REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE

THC63LVDM83R /THC63LVDM63R_Rev2.0
Switching Characteristics
Symbol
t_TCIT
t_TCP
t_TCH
t_TCL
t_TCD
t_TS
t_TH
t_LVT
t_TOP1
Parameter
CLK IN Transition time
CLK IN Period
CLK IN High Time
CLK IN Low Time
CLK IN to TCLK+/- Delay
TTL Data Setup to CLK IN
TTL Data Hold from CKL IN
LVDS Transition Time
Output Data Position0 (T=11.76ns)
t_TOP0 Output Data Position1 (T=11.76ns)
t_TOP6 Output Data Position2 (T=11.76ns)
t_TOP5 Output Data Position3(T=11.76ns)
t_TOP4 Output Data Position4 (T=11.76ns)
t_TOP3 Output Data Position5 (T=11.76ns)
t_TOP2
t_TPLL
Output Data Position6 (T=11.76ns)
Phase Lock Loop Set
Min.
11.76
0.35T
0.35T
2.5
2.5
-0.2
V_CC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Typ.
Max.
Units
5.0 ns
T
50.0
ns
0.5T
0.65T
ns
0.5T
0.65T
ns
2T/7
ns
ns
ns
0.6
1.5
ns
0.0
+0.2
ns
T-7-- _{– 0.2}
T-7--
T-7-- _{+ 0.2}
ns
2T-7-- – 0.2
2 ^T-7--
2T-7-- + 0.2
ns
3T-7-- – 0.2
3 ^T-7--
3T-7-- + 0.2
ns
4T-7-- – 0.2
4 ^T-7--
4T-7-- + 0.2
ns
5T-7-- – 0.2
5 ^T-7--
5T-7-- + 0.2
ns
6T-7-- – 0.2
6 ^T-7--
6T-7-- + 0.2
ns
10.0
ms
AC Timing Diagrams
TTL Input
90%
CLK IN _10%
LVDS Output
V_diff=(TA+)-(TA-)
TA+
5pF _100Ω
TA-
LVDS Output Load
V_diff
t_TCIT
80%
20%
t_LVT
90%
10%
t_TCIT
80%
20%
t_LVT
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.