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THC63LVD103D_15 Datasheet, PDF (8/18 Pages) THine Electronics, Inc. – 160MHz 30bit COLOR LVDS TRANSMITTER
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THC63LVD103D_Rev.4.01_E
LVCMOS/TTL & LVDS Transmitter AC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Unit
tTCIT CLK IN Transition Time
-
-
5.0
ns
tTCP CLK IN Period
6.25
T
125
ns
tTCH CLK IN High Time
0.35T
0.5T
0.65T
ns
tTCL CLK IN Low Time
0.35T
0.5T
0.65T
ns
tTCD CLK IN to TCLK+/- Delay
-
3T
-
ns
tTS LVCMOS/TTL Data Setup to CLK IN
2.0
-
-
ns
tTH LVCMOS/TTL Data Hold from CLK IN
0.0
-
-
ns
tLVT LVDS Transition Time
-
0.6
1.5
ns
tTOP1 Output Data Position0 (T=6.25ns ~ 20ns)
-0.15
0.0
+0.15
ns
tTop0 Output Data Position1 (T=6.25ns ~ 20ns)
T/7-0.15
T/7
T/7+0.15
ns
tTop6 Output Data Position2 (T=6.25ns ~ 20ns)
2T/7-0.15 2T/7 2T/7+0.15
ns
tTop5 Output Data Position3 (T=6.25ns ~ 20ns)
3T/7-0.15 3T/7 3T/7+0.15
ns
tTop4 Output Data Position4 (T=6.25ns ~ 20ns)
4T/7-0.15 4T/7 4T/7+0.15
ns
tTop3 Output Data Position5 (T=6.25ns ~ 20ns)
5T/7-0.15 5T/7 5T/7+0.15
ns
tTop2 Output Data Position6 (T=6.25ns ~ 20ns)
6T/7-0.15 6T/7 6T/7+0.15
ns
tTPLL Phase Lock Loop Set
-
-
10.0
ms
*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC
Table 7. LVCMOS/TTL & LVDS Transmitter AC Specifications
LVCMOS/TTL Input
90%
CLK IN 10%
90%
10%
t
TCIT
tTCIT
Figure 5. CLKIN Transmission Time
LVDS Output
LVDS Output Load
Figure 6. LVDS Output Load and Transmission Time
Copyright©2015 THine Electronics, Inc.
7
THine Electronics, Inc.
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