THC63LVDM83D Datasheet, PDF (7/12 Pages) THine Electronics, Inc. – REDUCED SWING LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE

THC63LVDM83D_Rev.3.1_E
Switching Characteristics
Symbol
t_TCIT
t_TCP
t_TCH
t_TCL
t_TCD
t_TS
t_TH
t_LVT
t_TOP1
Parameter
CLK IN Transition time
CLK IN Period
CLK IN High Time
CLK IN Low Time
CLK IN to TCLK+/- Delay
TTL Data Setup to CLK IN
TTL Data Hold from CLK IN
LVDS Transition Time
Output Data Position0 (T=6.25ns~20ns)
t_TOP0 Output Data Position1 (T=6.25ns~20ns)
t_TOP6 Output Data Position2 (T=6.25ns~20ns)
t_TOP5 Output Data Position3(T=6.25ns~20ns)
t_TOP4 Output Data Position4 (T=6.25ns~20ns)
t_TOP3 Output Data Position5 (T=6.25ns~20ns)
t_TOP2
t_TPLL
Output Data Position6 (T=6.25ns~20ns)
Phase Lock Loop Set
Min.
6.25
0.35T
0.35T
2.0
0.0
-0.15
V_CC = 3.0V ~ 3.6V, Ta = 0°C ~ +70 °C
Typ.
Max.
Units
5.0
ns
T
125
ns
0.5T
0.65T
ns
0.5T
0.65T
ns
3T
ns
ns
ns
0.6
1.5
ns
0.0
+0.15
ns
T---
7
–
0.15
T---
T--- _{+ 0.15}
ns
7
7
2
T---
7
–
0.15
2 ^T---
2T--- + 0.15
ns
7
7
3T--- – 0.15
7
3 ^T---
3T--- + 0.15
ns
7
7
4T--- – 0.15
7
4 ^T---
4T--- + 0.15
ns
7
7
5T--- – 0.15
7
5 ^T---
5T--- + 0.15
ns
7
7
6T--- – 0.15
7
6 ^T---
6T--- + 0.15
ns
7
7
10.0
ms
AC Timing Diagrams
TTL Input
90%
CLK IN _10%
90%
10%
t_TCIT
t_TCIT
Fig2. CLKIN Transition Time
LVDS Output
V_diff=(TA+)-(TA-)
TA+
V_diff
5pF _100Ω
TA-
LVDS Output Load
80%
20%
t_LVT
80%
20%
t_LVT
Fig3. LVDS Output Load and Transition Time
Copyright©2011 THine Electronics, Inc.
7/12
THine Electronics, Inc.