THCV219_16 Datasheet, PDF (6/18 Pages) THine Electronics, Inc. – V-by-One HS High-speed Video Data Transmitter

Data Enable
Figure 2 is the conceptual diagram of the basic operation of the chipset.THCV220 in Figure 2 is an example of
V-by-One® HS Receiver.
There are some requirements for DE. Figure 3 shows the timing diagram of it.
THCV219
R/G/B
CONT
1
V,HSYNC
CTL
0
THCV220
R/G/B
CONT
DE=1, R/G/B,CONT
DE=0, CTL
VSYNC
HSYNC
DE=1, V,HSYNC=Fixed
DE=0, V,HSYNC
DE
CTL are particular assigned bit among R/G/B,CONT
that can carry arbitrary data during DE=0 period.
Figure 2. Conceptual diagram of the basic operation of the chipset
THCV219
t_DEH
t_DEL
Input
CLKIN
(RF=H)
DE
Low
HSYNC
VSYNC
Valid Data
RGB
CONT
Invalid
High
Invalid
Valid Data
High
Invalid
Low
Valid Data
Valid Data
Invalid
Low
Valid Data
High
Invalid
Invalid Valid Data
THCV220
t_DEH
t_DEL
Output*
CLKOUT
(RF=H)
DE
Low
High
High
Low
Low
High
HSYNC
VSYNC
RGB
CONT
Valid Data
Keep the
last data
Keep the last data
of DE=L period
Valid Data
Keep the last data
of DE=L period
Valid Data
Valid Data
Keep the
last data
Valid Data
Keep the last data
of DE=L period
Keep the
last data Valid Data
Particular assigned bit ‘CTL’ is transmitted expect the first
and last pixel of Blanking period. Ohters are Low fixed.
*Refer to the data sheet of THCV220 for output operation
Figure 3. Data and synchronizing signals transmission timing diagram
symbol
tDEH
tDEL
Table 1. DE requirement
Parameter
min.
typ.
DE=High Duration
2tTCIP
DE=Low Duration
2tTCIP
max.
Unit
sec
sec
THCV219_Rev.2.20_E
Copyright©2016 THine Electronics, Inc.
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