THC63LVD104C Datasheet, PDF (3/13 Pages) THine Electronics, Inc. – 112MHz 30Bits COLOR LVDS Receiver

THC63LVD104C_Rev.2.1_E
THine
Pin Description
Pin Name
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
RE+,RE-
RCLK+, RCLK-
RA6 ~ RA0
RB6 ~ RB0
RC6 ~ RC0
RD6 ~ RD0
RE6 ~ RE0
TEST
Pin #
50, 49
52, 51
55, 54
60, 59
62, 61
57, 56
40,41,42,43,45,46,47
32,33,34,35,36,38,39
22,24,25,26,27,28,29
14,15,17,18,19,20,21
6,7,8,10,11,12,13
2
PD
3
OE
4
R/F
VCC
CLKOUT
GND
LVCC
LGND
PVCC
PGND
5
9,23,37,48
31
1,16,30,44
53
58
64
63
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
Power
OUT
Ground
Power
Ground
Power
Ground
Description
LVDS Data In.
LVDS Clock In.
CMOS/TTL Data Outputs.
Test pin, must be “L” for normal operation.
H: Normal operation,
L: Power down (all outputs are “L”)
H: Output enable (Normal operation).
L: Output disable(all outputs are Hi-Z)
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
Power Supply Pins for TTL outputs and digital circuitry.
Clock out.
Ground Pins for TTL outputs and digital circuitry.
Power Supply Pin for LVDS inputs.
Ground Pin for LVDS inputs.
Power Supply Pin for PLL circuitry.
Ground Pin for PLL circuitry.
PD
R/F
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
** Rxn
x = A,B,C,D,E
n = 0,1,2,3,4,5,6
Data Outputs
OE
(Rxn)
CLKOUT
0
Hi-Z
Hi-Z
1
All 0
Fixed Low
0
Hi-Z
Hi-Z
1
All 0
Fixed Low
0
Hi-Z
Hi-Z
1
Data Out The falling edge closer to the center of the data eye.
0
Hi-Z
Hi-Z
1
Data Out The rising edge closer to the center of the data eye.
Copyright©2010 THine Electronics, Inc.
3/13
THine Electronics, Inc.