THM3561 Datasheet, PDF (14/21 Pages) THine Electronics, Inc. – Stepping Motor Driver with LVDS Interface

THM3561_Rev1.01_E
Functional Description (continued)
The internal circuit of this product operates on VREG5 voltage. However, in the case of using a host device of a
3.3V system (microcontroller etc.), the device can be directly connected to the pre-stage interface by supplying 3.3V
to the VIO pin. The target pre-stage interface terminal is the SCK / CSn / SI / OMODE input pin and SO output pin in
4-wire CMOS mode.
When the host device, which is directly connected to the pre-stage interface, is a 5V system, the VIO pin is shorted
to VREG5 pin over the substrate. In this case, the pre-stage interface pin operates on a 5V system (using VREG5
power supply).
Power Down (PDWN)
This product can be changed to a low power state (power down) on setting the PDWN pin to High level. The
internal circuit gets reset on setting this pin to High level and the resistor and internal step change reverts to the initial
state. All driver outputs change to OFF.
In the case of using this pin as a reset pin, the condenser connected to VREG5 is discharged and hence, it is
recommended that the PDWN pin be kept at High level for about 100ms. If the discharging of the condenser is
inadequate, an operation such as an unstable interface output may occur temporarily.
Internal Oscillator Frequency Select (ROSC)
This device contains an oscillator for internal logic circuit.
This pin is usually connected to GND with a 47kohm pull-down resistor for the oscillator reference current.
FAULTn Pin
The FAULTn pin outputs Low level at the time of detecting Over Current Protection function (OCP) and detecting
Thermal Shutdown function (TSD). It generally becomes an open drain output and becomes High-Z. In the case of
using this pin for detection of abnormalities, use this by pulling up to the power supply line below 5V.
Driver Operation Mode
The operation mode of the stepping motor control can be selected by setting DMODE pin. Perform the settings as
set out in the table below according to the operation mode to be used.
Table 15. Operation Mode (DMODE) Setting
DMODE
Description
0
Phase input mode
1
Clock input mode
[Phase input mode]
Functions as phase input mode based on fixing the DMODE pin to Low level. In phase input mode, the value set in
the register is directly reflected on output.
[Clock input mode]
Functions as clock input mode based on fixing the DMODE terminal to High level. In the clock input mode,
internal step advances and output is changed according to the step when CK bit changes from 0 to 1. Step direction
and excitation mode can be selected by the PEM bit. The excitation mode corresponds to phase 1 excitation / phase 2
excitation / phase 1-2 excitations. For resistor details, see the Register Map section.
* The behavior in the case of change-over of mode during operation cannot be guaranteed.
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