THL3512 Datasheet, PDF (10/16 Pages) THine Electronics, Inc. – The THL3512 is an LED driver with 24 channel opendrain

THL3512_Rev.1.02_E
3-wire Serial CMOS Level Input
When the MODE pin is set to high, the serial interface for writing to registers becomes 3-wire serial CMOS level input.
The chip select (CSn), serial clock (SCK), serial data (SI) of 3-wire serial CMOS level input are input to the SCL_INn
pin, the SCL_INp pin, the SDA_IN pin respectively. The SDA_INn must be tied to low.
- While the CSn stays low, the data input SI is latched by rising edges of the clock input SCK.
- The data latched by the first clock rising edge after the CSn falls is assigned the “first bit“.
- The “Last Byte” is written to a register when the CSn rises after Bit0 (in other words, “Last Byte” will not be written to
a register until the CSn rises).
- If the CSn rises in the middle of a byte, the byte is not written to a register, then the communication resumes from “1st
Byte” when the CSn falls next.
< 3-wire Serial CMOS Level Input >
SCL_INn (CSn)
SCL_INp (SCK)
7654321076
76543210
SDA_INp (SI)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
“1st Byte“
“2nd Byte“
“Last Byte“
2-pair serial LVDS
When the MODE pin is set to low, the serial interface for writing to registers becomes 2-pair serial LVDS input
(SCL_INp/SCL_INn, SDA_INp/SDA_INn).
- The data input SDA_IN is latched by rising edges of the clock input SCL_IN.
- A falling transition of the SDA_IN while the SCL_IN is high is defined as ”Header Condition“, and the data latched by
the first clock rising edge after the “Header Condition” is assigned the “first bit“. Except ”Header Condition”, the transi-
tions of the data input SDA_IN are allowed while the clock input SCL_IN is low.
- The “Last Byte” is written to a register at the reception of an active-low pulse “End Pulse” (actually, “Last Byte” is
written to a register at the rising edge of the “End Pulse“). When the “End Pulse” rises, the data output SDA_OUT must
be high.
- If the ”Header Condition” is received in the middle of a byte, the byte is not written to a register, then the communica-
tion resumes from “1st Byte“.
SCL_IN
< 2-pair serial LVDS input >
7654321076
7 6 5 4 3 2 1 0 ^{End Pulse}
SDA_IN
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Header Condition
“1st Byte“
“2nd Byte“
“Last Byte“
* The 3-wire to 2-pair bridge function can convert 3-wire serial output from the host such as micro-controller or CPU to
2-pair sereal LVDS. Please refer to the section “3-wire to 2-pair bridge function” for details.
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