THC63LVDR84B Datasheet, PDF (1/10 Pages) THine Electronics, Inc. – LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER (Rising Edge Clock)

THC63LVDR84B_Rev.2.2_E
THC63LVDR84B
LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER (Rising Edge Clock)
General Description
The THC63LVDR84B receiver supports wide VCC
range(2.5~3.6V). At single 2.5V supply, the
THC63LVDR84B reduces EMI and power consump-
tion.
The THC63LVDR84B receiver convert the four
LVDS(Low Voltage Differential Signaling) data streams
back into 24bits of CMOS/TTL data with rising edge
clock.
At a transmit clock frequency of 85MHz, 24bits of RGB
data and 4bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
a rate of 2.3Gbps.
Features
• Wide dot clock and Wide VCC range:
V CC[V]
Clock Frequency[MHz]
15 to 20 20 to 70 70 to 85
2.5 to 2.7 n/a available n/a
2.7 to 3.0 available available n/a
3.0 to 3.6 available available available
n/a : not available
• Rising Edge Clock
• PLL requires No external components
• Rx power consumption < 80mW @VCC 2.5V,
65MHz Grayscale
• Power-Down Mode
• Low profile 56 Lead TSSOP Package
• Pin compatible with DS90CR286ATMD
Block Diagram
RA +/-
DATA
(LVDS)
RB +/-
RC +/-
RD +/-
THC63LVDR84B
CMOS/TTL
OUTPUT
7 _RA0-6
7 _RB0-6
7
RC0-6
7 _RD0-6
CLOCK
(LVDS) ^{RCLK +/-}
15 to 85MHz
RECEIVER
PLL
CLOCK OUT
(15 to 85MHz)
/PDWN
(105-595Mbit/On Each LVDS Channel)
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.