ICL7660 Datasheet, PDF (8/10 Pages) Intersil Corporation – CMOS Voltage Converters

ICL7660, ICL7660A
every cycle. In a typical application where f_OSC = 10kHz and
C = C₁ = C₂ = 10 F:
1
R_O
2 (23) +
(5
10³) (10^-5) ^{+ 4 (ESRC1) + ESRC2}
R_O 46 + 20 + 5 (ESR_C)
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f_PUMP C₁) term, rendering an
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10
1
R_O
2 (23) +
(5
10³) (10-⁵) ^{+ 4 (ESRC1) + ESRC2}
R_O/ 46 + 20 + 5 (ESR_C)
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f_PUMP C₁) term, rendering an
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 14. Segment A is the voltage drop across the ESR of
C₂ at the instant it goes from being charged by C₁ (current
flow into C₂) to being discharged through the load (current
flowing out of C₂). The magnitude of this current change is
2 I_OUT, hence the total drop is 2 I_OUT eSR_C2V.
Segment B is the voltage change across C₂ during time t₂ ,
the half of the cycle when C₂ supplies current to the load.
The drop at B is l_OUT t2/C₂V. The peak-to-peak ripple
voltage is the sum of these voltage drops:
[ ] ^VRIPPLE
1
2 (f_PUMP) (C2) _{+ 2 (ESRC2)}
I_OUT
Again, a low ESR capacitor will reset in a higher
performance output.
Paralleling Devices
Any number of ICL7660 and ICL7660A voltage converters
may be paralleled to reduce output resistance. The reservoir
capacitor, C₂ , serves all devices while each device requires
its own pump capacitor, C₁ . The resultant output resistance
would be approximately:
R_OUT =
R_OUT (of ICL7660/ICL7660A)
n (number of devices)
Cascading Devices
The ICL7660 and ICL7660A may be cascaded as shown to
produced larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
V_OUT = -n (V_IN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660
and ICL7660A R_OUT values.
Changing the ICL7660/ICL7660A Oscillator
Frequency
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an
external clock, as shown in Figure 17. In order to prevent
possible device latchup, a 1k resistor must be used in
series with the clock output. In a situation where the
designer has generated the external clock frequency using
TTL logic, the addition of a 10k pullup resistor to V+ supply
is required. Note that the pump frequency with external
clocking, as with internal clocking, will be ¹/₂ of the clock
frequency. Output transitions occur on the positive-going
edge of the clock.
10 F ⁺
-
1
8
2
ICL7660
7
3 ^ICL7660A 6
4
5
V+
V+
1k
CMOS
GATE
-
V_OUT
+F ¹⁰
FIGURE 17. EXTERNAL CLOCKING
It is also possible to increase the conversion efficiency of the
ICL7660 and ICL7660A at low load levels by lowering the
oscillator frequency. This reduces the switching losses, and is
shown in Figure 18. However, lowering the oscillator
frequency will cause an undesirable increase in the
impedance of the pump (C₁) and reservoir (C₂) capacitors;
this is overcome by increasing the values of C₁ and C₂ by the
same factor that the frequency has been reduced. For
example, the addition of a 100pF capacitor between pin 7
(OSC) and V+ will lower the oscillator frequency to 1kHz from
its nominal frequency of 10kHz (a multiple of 10), and thereby
necessitate a corresponding increase in the value of C₁ and
C₂ (from 10 F to 100 F).