73S1210F Datasheet, PDF (77/126 Pages) Teridian Semiconductor Corporation – Self-Contained Smart Card Reader with PINpad and Power Management

DS_1210F_001
73S1210F Data Sheet
VCCSEL
bits
VCC
VCCOK
RSTCRD
RST
t3
CLK
IO
t1
t2
t4
tto
t1: The time from setting VCCSEL bits until VCCOK = 1.
tto: The time from setting VCCSEL bits until VCCTMR times out. At t1 (if RDYST = 1) or tto (if RDYST = 0),
activation starts. It is suggested to have RDYST = 0 and use the VCCTMR interrupt to let MPU know when
sequence is starting.
t2: time from start of activation (no external indication) until IO goes into reception mode (= 1). This is approximately
4 SCCLK (or SCECLK) clock cycles.
t3: minimum one half of ETU period.
t4: ETU period.
Note that in Sync mode, IO as input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK,
either from the card or from the 73S1210F. The RST signal to the card is directly controlled by the RSTCRD bit
(non-inverted) via the MPU and is shown as an example of a possible RST pattern.
Figure 20: Synchronous Activation
IO reception on
RST
2
5
CLK
CLKOFF
1
CLKLVL
RLength Count
RLenght = 1
Count MAX
7
Rlength Interrupt
3
4
TX/RXB Mode bit
6
(TX = '1')
t1
1. Clear CLKOFF after Card is in reception mode.
2. Set RST bit.
3. Interrupt is generated when Rlength counter is MAX.
4. Read and clear Interrupt.
5. Clear RST bit.
6. Toggle TX/RXB to reset bit counter.
7. Reload RLength Counter.
t1. CLK wll start at least 1/2 ETU after CLKOFF is set low
when CLKLVL = 0
Figure 21: Example of Sync Mode Operation: Generating/Reading ATR Signals
Rev. 1.4
77