73S1217F Datasheet, PDF (49/140 Pages) Teridian Semiconductor Corporation – Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More

DS_1217F_002
Timer/Counter Control Register (TCON): 0x88 Å 0x00
Table 42: The TCON Register
MSB
TF1 TR1 TF0 TR0 IE1
IT1
IE0
73S1217F Data Sheet
LSB
IT0
Bit
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Function
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when
an interrupt is processed.
Timer 1 Run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag
can be cleared by software and is automatically cleared when an
interrupt is processed.
Timer 0 Run control bit. If cleared, Timer 0 stops.
External Interrupt 1 edge flag.
External interrupt 1 type control bit.
External Interrupt 0 edge flag.
External Interrupt 0 type control bit.
1.7.8 WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles.
After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a
16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once
the watchdog starts, it cannot be stopped unless the internal reset signal becomes active.
Note: It is recommended to use the hardware watchdog timer instead of the software watchdog
timer (refer to the RTC description).
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register
enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6
in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing
the state of the WDT timer.
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request
signal from becoming active. This requirement imposes an obligation on the programmer to issue two
instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay
allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has
not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of
the WDTREL register and WDT is automatically reset.
Rev. 1.2
49