73S1209F Datasheet, PDF (47/123 Pages) Teridian Semiconductor Corporation – Self-Contained PINpad, Smart Card Reader IC UART to ISO7816 / EMV Bridge IC

DS_1209F_004
73S1209F Data Sheet
Interrupt Enable 0 Register (IEN0): 0xA8 Å 0x00
Table 44: The IEN0 Register
MSB
LSB
EAL WDT ET2 ES0 ET1 EX1 ET0 EX0
Bit
IEN0.7
IEN0.6
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
Symbol
Function
EAL EAL = 0 – disable all interrupts.
WDT Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly before
SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT
is reset by hardware 12 clock cycles after it has been set.
–
ES0 ES0 = 0 – disable serial channel 0 interrupt.
ET1 ET1 = 0 – disable timer 1 overflow interrupt.
EX1 EX1 = 0 – disable external interrupt 1.
ET0 ET0 = 0 – disable timer 0 overflow interrupt.
EX0 EX0 = 0 – disable external interrupt 0.
Interrupt Enable 1 Register (IEN1): 0xB8 Å 0x00
Table 45: The IEN1 Register
MSB
LSB
–
SWDT EX6
EX5
EX4
EX3
EX2
Bit
IEN1.7
IEN1.6
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
Symbol
–
SWDT
EX6
EX5
EX4
EX3
EX2
–
Function
Watchdog timer start/refresh flag. Set to activate/refresh the watchdog
timer. When directly set after setting WDT, a watchdog timer refresh is
performed. Bit SWDT is reset by the hardware 12 clock cycles after it has
been set.
EX6 = 0 – disable external interrupt 6.
EX5 = 0 – disable external interrupt 5.
EX4 = 0 – disable external interrupt 4.
EX3 = 0 – disable external interrupt 3.
EX2 = 0 – disable external interrupt 2.
Rev. 1.2
47