78P2351R Datasheet, PDF (4/31 Pages) Teridian Semiconductor Corporation – Serial 155M NRZ to CMI Converter

FUNCTIONAL DESCRIPTION
The 78P2351R contains all the necessary transmit
and receive circuitry for connection between
155.52Mbit/s NRZ data sources (STS-3/STM-1) and
CMI encoded electrical interfaces (ES1/STM-1e).
The 78P2351R system interface mimics a 3.3V
optical transceiver module and only requires a
reference clock and wideband transformer to
complete the electrical interface. The chip can be
controlled via control pins or serial port register
settings.
In hardware mode (pin control) the SPSL pin must
be low. Additionally, the following unused pins
must be set accordingly:
SDO pin must be tied low
SDI pin must be tied low
SEN pin must be tied high
In software mode (SPSL pin high), control pins set
register defaults upon power-up or reset. The
78P2351R can then be configured via the 4-wire
serial control interface. See Pin Descriptions
section for more information.
REFERENCE CLOCK
The 78P2351R requires a reference clock supplied
to the CKREFP/N pins. For reference frequencies of
19.44MHz or 77.76MHz, the device accepts a single
ended CMOS level input at CKREFP (with CKREFN
pin tied to ground). For reference frequency of
155.52MHz, the device accepts a differential
LVPECL clock input at CKREFP/N. The frequency
of this reference input is selected by either the CKSL
control pin or register bit as follows:
CKSL pin
Low
Float
High
CKSL[1:0] bits
00
10
11
Reference
Frequency
19.44MHz
77.76MHz
155.52MHz
RECEIVER OPERATION
The receiver accepts an ITU-T G.703 compliant CMI
encoded signal at 155.52Mbit/s from the RXP/N
inputs. When properly terminated and transformer-
coupled to the line, the receiver can handle over
12.7dB of cable loss. The receiver’s jitter tolerance
exceeds all relevant standards even with 12.7dB
worth of cable attenuation and inter-symbol
interference (ISI). See Receiver Jitter Tolerance
section for more info.
78P2351R
Serial 155M
NRZ to CMI Converter
The recovered CMI signal first enters an AGC and
an adaptive equalizer designed to overcome inter-
symbol interference caused by long cable lengths.
The variable gain differential amplifier automatically
controls the gain to maintain a constant voltage level
output regardless of the input voltage level.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a Delay Locked Loop (DLL), which
utilizes a line-rate reference frequency derived from
the clock applied to the CKREFP/N pins. After the
clock and data have been recovered, the data is
decoded to binary by the CMI decoder. The
SODP/N pins output the recovered NRZ data at
LVPECL levels.
Receiver Monitor Mode
The SCK_MON pin or MON register bit puts the
receiver in monitor mode and adds approximately
20dB of flat gain to the receive signal before
equalization. Rx Monitor Mode can handle 20dB of
flat loss typical of monitoring points with up to 6dB
(typical 225ft) of cable loss. Note that Loss of Signal
detection is disabled during Rx Monitor Mode.
Receive Loss of Signal Detect
The 78P2351R includes a Loss of Signal (LOS)
detector. When the peak value of the received
signal is less than approximately 19dB below
nominal for approximately 110 UI, Receive Loss of
Signal is asserted. The Rx LOS signal is cleared
when the received signal is greater than
approximately 18dB below nominal for 110 UI.
During Rx LOS conditions, the receive clock will
remain on the last phase tap of the Rx DLL
outputting a stable clock while the receive data
outputs are squelched and held at logic ‘0’.
Note: Rx Loss of Signal detection is disabled
during Local Loopback and Receive Monitor
Modes.
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2006 Teridian Semiconductor Corporation
Rev. 2.1