73M1903 Datasheet, PDF (4/46 Pages) Teridian Semiconductor Corporation – Modem Analog Front End

73M1903 Data Sheet
DS_1903_032
1 Signal Description
The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the
same pin out. The following table describes the function of each pin. There are two pairs of power
supply pins, VPA (analog) and VPD (digital). They should be separately decoupled from the supply
source in order to isolate digital noise from the analog circuits internal to the chip. Failure to adequately
isolate and decouple these supplies will compromise device performance.
Pin Name
VND
VNA
VPD
VPA
VPPLL
VNPLL
RST
OSCIN
OSCOUT
GPIO(0-7)
VREF
RXAP
RXAN
TXAP
TXAN
SCLK
SDOUT
SDIN
FS
TYPE
SckMode
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Type
GND
GND
PWR
PWR
PWR
PWR
I
I
O
I/O
O
I
I
O
O
O
32QFN
Pin #
1,22
16
2,25
10
20
17
9
19
18
3, 4, 5, 6,
23,
24,30,31
13
15
14
12
11
8
20VT
Pin#
2,18
13
3
8
17
14
7
16
15
N/A
6
12
11
10
9
5
Description
Negative Digital Ground
Negative Analog Ground
Positive Digital Supply
Positive Analog Supply
Positive PLL Supply, shared with VPD
Negative PLL Ground
Master reset. When this pin is a logic 0 all registers are
reset to their default states; Weak-pulled high- default.
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
Crystal oscillator circuit output pin.
Software definable digital input/output pins. Not available in
the 20VT (TSSOP) package.
Reference voltage pin (Reflects VREF).
Receive analog positive input.
Receive analog negative input.
Transmit analog positive output.
Transmit analog negative output.
Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576 MHz for Fs=9.6 kHz)
O
32
1 Serial data output (or input to the host).
I
29
20 Serial data input (or output from the host).
O
7
4 Frame synchronization. (Active Low)
I
27
19 Type of frame sync. Open, weak-pulled high = early
(mode1); tied low = late (mode0).
Controls the SCLK behavior after FS. Open, weak-pulled
I
28
NA high = SCLK Continuous; tied low = 32 clocks per R/W
cycle. Not available in 20VT.
4
Rev. 2.0