73S1215F Datasheet, PDF (31/136 Pages) Teridian Semiconductor Corporation – 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More

DS_1215F_003
73S1215F Data Sheet
Master Clock Control Register (MCLKCtl): 0x8F Å 0x0A
MSB
HSOEN KBEN
Table 18: The MCLKCtl Register
SCEN USBEN 32KEN MCT.2 MCT.1
LSB
MCT.0
Bit
MCLKCtl.7
MCLKCtl.6
MCLKCtl.5
MCLKCtl.4
MCLKCtl.3
MCLKCtl.2
MCLKCtl.1
MCLKCtl.0
Symbol
HSOEN*
KBEN
SCEN
USBEN
32KEN
MCT.2
MCT.1
MCT.0
Function
High-speed oscillator enable. When set = 1, disables the high-speed
crystal oscillator and VCO/PLL system. This bit is not changed when the
PWRDN bit is set but the oscillator/VCO/PLL is disabled.
1 = Disable the keypad logic clock. This bit is not changed in PWRDN
mode but the function is disabled.
1 = Disable the smart card logic clock. This bit is not changed in PWRDN
mode but the function is disabled. Interrupt logic for card insertion/removal
remains operable even with smart card clock disabled.
1 = Disable the USB logic clock. This bit is not changed in PWRDN mode
but the function is disabled.
1 = Disable the 32Khz oscillator. This function is not affected by PWRDN
mode. Note: This bit must be set if there is no 32KHz crystal or the 44 pin
package is used. Some internal clocks and circuits will not run if the
oscillator is enabled and no crystal is connected.
This value determines the ratio of the VCO frequency (MCLK) to the high-
speed crystal oscillator frequency such that:
MCLK = (MCount*2 + 4)*Fxtal. The default value is MCount = 2h such that
MCLK = (2*2 + 4)*12.00MHz = 96MHz.
*Note: The HSOEN bit should never be set under normal circumstances. Power down control should
only be initiated via use of the PWRDN bit in MISCtl0.
Rev. 1.4
31