78Q2120C Datasheet, PDF (26/35 Pages) Teridian Semiconductor Corporation – 10/100BASE-TX Transceiver

78Q2120C
10/100BASE-TX
Transceiver
100BASE-TX System Timing
System timing requirements for 100BASE-TX operation are listed in Table 24-2 of Clause 24 of IEEE 802.3.
PARAMETER
CONDITION
NOM
UNIT
TX_EN Sampled to first bit of “J” on MDI
output
First bit of “J” on MDI input to CRS assert
12
BT
16
BT
First bit of “T” on MDI input to CRS
de-assert
First bit of “J” on MDI input to COL assert
First bit of “T” on MDI input to COL
de-assert
23
BT
20
BT
24
BT
TX_EN Sampled to CRS assert
TX_EN sampled to CRS de-assert
RPTR = low
RPTR = low
6
BT
6
BT
10BASE-T System Timing
PARAMETER
CONDITION
MIN
NOM MAX
TX_EN (MII) to TD Delay
6
RD to RXD at (MII) Delay
6
Collision delay
9
SQE test wait
1
SQE test duration
1
Jabber on-time*
20
150
Jabber off-time*
250
750
* Guarantee by design. The specifications in the following table are included for information only.
UNIT
BT
BT
BT
µs
µs
ms
ms
Page: 26 of 35
© 2009 Teridian Semiconductor Corporation
Rev 1.3