73K324L Datasheet, PDF (15/30 Pages) List of Unclassifed Manufacturers – CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem

73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem
DATA SHEET
CONTROL REGISTER 3
CR3
101
D7
TXDALT
D6
TRISTATE
TX/RXCLK
BIT NO.
NAME
D3, D2,
D1,D0
D4
Transmit
Attenuator
Receive
Gain Boost
(18 dB)
D5
Not Used
D6
Tristate
TXCLK/RXCLK
D7
TXDALT
D5
D4
D3
D2
D1
D0
0
RECEIVE TRANSMIT TRANSMIT TRANSMIT TRANSMIT
ENABLE
ATTEN.
ATTEN.
ATTEN.
ATTEN.
BOOST
3
2
1
0
CONDITION DESCRIPTION
D3 D2 D1 D0
0 0 0 0- Sets the attenuation level of the transmitted signal in 1 dB
1 1 1 1 steps. The default (D3-D0=0100) is for a transmit level of
–10 dBm0. The total range is 16 dB.
0
18 dB receive front end boost is not used.
1
Boost is in the path. This boost does not change
reference levels. It is used to extend dynamic range by
compensating for internally generated noise when
receiving weak signals. The receive level detect signal
and knowledge of the hybrid and transmit attenuator
setting will determine when boost should be enabled.
0
Not used. Only write zeros this location.
0
TXCLK, RXCLK outputs driven
1
TXCLK, RXCLK outputs in Tristate mode
Spec. Reg. bit D3=1 Alternate TX data source. See Special Register.
ID REGISTER
SPECIAL REGISTER
SR
D7
D6
101
0
TXBAUD
CLOCK
BIT NO.
D7, D4, D0
D6
NAME
TXBAUD
CLK
D5
RXUNDSCR
DATA
D5
D4
D3
D2
D1
D0
RXUN-
DSCR
DATA
0
TXD
SIGNAL
SIGNAL
0
SOURCE QUALITY QUALITY
LEVEL
LEVEL
SELECT1 SELECT0
DESCRIPTION
NOT USED AT THIS TIME. Only write ZEROs to these bits.
TXBAUD clock is the transmit baud-synchronous clock that can be used to
synchronize the input of arbitrary quad/di-bit patterns. The rising edge of
TXBAUD signals the latching of a baud-worth of data internally. Synchronous
data to be entered via the TXDALT bit, CR3 bit D7, should have data
transitions that start 1/2 bit period delayed from the TXBAUD clock edges.
This bit outputs the data received before going to the descrambler. This is
useful for sending special unscrambled patterns that can be used for signaling.
Page: 15 of 30
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1