73S8024RN Datasheet, PDF (10/27 Pages) Teridian Semiconductor Corporation – Low Cost Smart Card Interface

73S8024RN Data Sheet
DS_8024RN_020
7 Activation Sequence
The 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the
application of V_DD > V_DDF. No activation is allowed at this time. The CMDVCC (edge triggered) must then
be set low to activate the card. In order to initiate activation, the card must be present; there can be no
over-temperature fault or no V_DD fault.
The following steps show the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low while the RSTIN is low:
• CMDVCC is set low.
• Next, the internal V_CC control circuit checks the presence of V_CC at the end of t₁. In normal operation,
the voltage V_CC to the card becomes valid during t₁. If V_CC does not become valid, the OFF goes low
to report a fault to the system controller, and the power V_CC to the card is shut off.
• Turn I/O (AUX1, AUX2) to reception mode at the end of (t₂).
• CLK is applied to the card at the end of (t₃).
• RST is a copy of RSTIN after (t₄). RSTIN may be set high before t₄, however the sequencer will not
set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t₁
t₂
t₃
t₄
t₁ = 0.510 ms (timing by 1.5MHz internal Oscillator)
t₂ = 1.5μs, I/O goes to reception state
t₃ = >0.5μs, CLK starts
t₄ ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 2: Activation Sequence – RSTIN Low When CMDVCC Goes Low
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Rev. 1.8