78P2343JAT Datasheet, PDF (1/37 Pages) Teridian Semiconductor Corporation – 3-port E3/DS3/STS-1 LIU with Jitter Attenuator

DESCRIPTION
The 78P2343JAT is a low-power, 3-port
DS3/E3/STS1 Line Interface Unit (LIU) with
integrated Jitter Attenuator (JAT). It includes all the
required clock recovery and transmitter pulse
shaping functions for applications using 75-ohm
coaxial cable at distances up to 1350 feet. These
applications include DSLAMs, T1,3/E1,3 digital
multiplexers, SONET Add/Drop multiplexers, PDH
equipment, DS3 to Fiber optic and microwave
modems and ATM WAN access for routers and
switches.
The receiver recovers clock and data from a B3ZS
or HDB3 coded AMI signal. It can compensate for
over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
standard pulse shape requirements.
The
78P2343JAT includes optional B3ZS/HDB3 ENDEC
with a receive line code violation detector, loop-back
modes, Loss of Signal detector, clock polarity
selection, and the ability to receive a DSX3 monitor
signal.
STANDARDS
• Telcordia GR-499-CORE and GR-253-CORE
• ITU-T G.823, G.824, G.775, and G.703
• ETSI TBR-24, ETS 300 686, ETS 300 687, and
ETS EN 300 689
• ANSI T1.102-1993, T1.231-1997, T1.404-1994,
and T1.105.03b
BLOCK DIAGRAM
78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
DATA SHEET
FEATURES
JULY 2005
• Transmit and receive interfaces for E3, DS3 and
STS-1 applications
• Designed for use with 75 ohm coaxial cable
lengths up to 1350 ft
• Receives DS3-high and DSX3 monitor signals
• Local and Remote loopbacks
• Selectable B3ZS/HDB3 ENDEC with line code
violation detector
• Standards-based LOS detector
• Optional serial-port based mode selection and
channel status monitoring
• Adaptive digital clock recovery (uses line-rate
reference clock input)
• Receive output clock maintains nominal line-rate
frequency at all times
• Fully integrated Jitter Attenuation function
provided for all line rates (no external VCXO
required)
• Jitter Attenuator configurable for transmit or
receive path
• Transmit line fault monitor
• Requires no external current-setting resistor or
loop filter components
• Single 3.3V supply operation
• Standard and exposed pad 100-pin JEDEC
LQFP package options available
Controls Flags
TPOS
TNEG
TCLK
RPOS
RNEG
RCLK
Jitter
Attenuator
TCLKP
RCLKP
CKREF
RLBK
LBO E3 DS3
B3ZS /
HDB3
Encoder
Pulse
Shaper
ENDEC
TXEN
Transmit
Monitor
Attenuator
TXNW
LOUTP
LOUTN
B3ZS /
HDB3
Decoder
Power
Distribution
PDTX PDRX
CS
SCK
SDI
SDO
Data
Detector
Adaptive
Equalizer
AGC
LINP
LINN
Clock
Recovery
Signal
Detector
MON
LOS
LLBKA
LLBKB
Signals from
Adjacent Port
Each Channel
Control
Registers
Master
Bias
Generator
CKREF
Page 1 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2