U6225B Datasheet, PDF (8/12 Pages) TEMIC Semiconductors – 2.9 GHz PLL for SAT TV Receiver with Universal Bus

U6225B
TELEFUNKEN Semiconductors
3-Wire-Bus Description
When the U6225B-B is controlled via 3-wire bus format,
then DATA, CLOCK and ENABLE signals are fed into
the SDA, SCL and AS/ENA lines respectively. The dia-
gram ’3-WIRE-BUS PULSE DIAGRAM’ shows the data
format. The data consist of a single word, which contains
the programmable divider and switch information. Only
during the enable high period the data is clocked into the
internal data shift register on the negative clock transi-
tion. During enable low periods the clock input is
disabled. New data words are only accepted by the inter-
nal data latches from the shift register on a negative
transition of the enable signal when during the high period
of the enable exactly nineteen clock pulses were send.
The data sequence and the timing is described in the fol-
lowing diagrams.
In 3-wire-bus mode pin 11 becomes automatically the
Locksignal output. An improved lock detect circuit gen-
erates a flag when the loop has attained lock. ’In lock’ is
indicated by a low impedance state (on) of the open col-
lector output.
In 3-wire-bus mode there is always the high charge pump
current active. Only in I²C-bus mode the charge pump
current can be controlled.
The complete PLL function can be disabled by program-
ming a normally not used division ratio of zero. This
allows the tuner alignment by supplying the tuning volt-
age directly through the 30 V supply voltage of the tuner.
3-Wire-Bus Pulse Diagram
4 Bit
15 Bit scaling factor SF
Ports
P7 P6 P5 P4 MSB
LSB
SDA
SCL
AS / ENA
3-Wire-Bus Timing
Data
Figure 5.
LSB
95 10733
Clock
Enable
TL
Parameters
Set up time
Enable hold time
Clock width
Enable set up time
Enable between two transmissions
Data hold time
TS TC TH TSL
Figure 6.
Symbol
Min.
TS
2
TSL
2
TC
2
TL
10
TT
10
TH
2
TT
95 10734
Typ.
Unit
ms
ms
ms
ms
ms
ms
8 (12)
Rev. A1: 25.10.1995