U4256BM Datasheet, PDF (8/14 Pages) TEMIC Semiconductors – Frequency Synthesizer for Radio Tuning

U4256BM
The gain of DAC2 has a range of 0.7 x V(PDO) to The offset of DAC2 has a range of 0.5 to –0.6. This range
2.15 x V(PDO). V(PDO) is the PLL tuning voltage is divided into 64 steps. So one step is approximately
output. This range is divided into 256 steps. So one step 1.1V/63 = 17.2 m. The offset can be controlled by the
is approximately (2.15–0.7)/256 = 5.664 m. The gain can Bits 8 to 13 (O–2⁰ to O–2⁵) as following:
be controlled by the bits 0 to 7 (G–2⁰ to G–2⁷) as _{Offset DAC2 B13 B12 B11 B10 B9 B8}
following:
Gain
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DAC2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Approx.
B7 B6 B5 B4 B3 B2 B1 B0
0.7
00000000
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{0.70566 0 0 0 0 0 0 0 1}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{0.71133 0 0 0 0 0 0 1 0}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{0.71699 0 0 0 0 0 0 1 1}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _...
... ... ... ... ... ... ... ...
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{1.00019 0 0 1 1 0 1 0 1}
...
... ... ... ... ... ... ... ...
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{2.1386 1 1 1 1 1 1 0 1}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{2.14434 1 1 1 1 1 1 1 0}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{2.15m 1 1 1 1 1 1 1 1}
Approx.
0.5
0.4828
0.4656
0.4484
...
–0.0156
...
0.5656
–0.5828
–0.6
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
... ... ... ... ... ...
0
1
1
1
1
0
... ... ... ... ... ...
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
Input / Output Interface Circuits
PDO
PDO is the loop amplifier output of the PLL. The bipolar
output stage is a rail-to-rail amplifier.
PD
PD is the current charge pump output of the PLL. The
current can be controlled by setting the Bits IDP1, 2 and
IDP3, 4. The loop filter has to be designed corresponding
to the choosen pump current and the internal reference
frequency. A recommendation can be found in the
application circuit.
V5
14859
V5
C
PDO
PD
Figure 5.
8 (14)
Rev. A2, 03-Nov-98
Preliminary Information