U3900BM Datasheet, PDF (6/34 Pages) TEMIC Semiconductors – Programmable Telephone Audio Processor

U3900BM
2.1.5 Data Recovery and Buffer
The incoming serial data are stored and sent to the SSB
each 10 bits (1 start bit, 8 data, 1 stop bit ). When after a
start bit 8 data bits and a stop bit are received, an interrupt
is generated, the INT pin will become active, and data
ready interrupt bit is set in the status register (bit 3). The
received data is available in the CLID DATA register.
DATA
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
INT pin
Figure 3. Interrupt treatment for SLID DATA register
2.1.6
CLID: Logical Part
Command bits
CD_CD < 3...0 >
from serial bus
Command bit SCD
from serial bus
NCD
CD
FSK
signal
Carrier
detect
Demodulator
Serial
data
Data recovery
and
buffer
DATA
DR
Clock
Data ready
Clock
recovery
14605
From/to
demodulator analog filter
Figure 4. Block diagram for CLID logical part
14606
2.1.7 Carrier Detect, Bandpass Frequencies
Low Frequencies
High Frequencies
CD_CD<0>
0
1
0
1
CD_CD<1>
0
0
1
1
Value
290 Hz
515 Hz
770 Hz
1000 Hz
CD_CD<2>
0
1
0
1
CD_CD<3>
0
0
1
1
Value
3400 Hz
3100 Hz
2665 Hz
1700 Hz
6 (34)
Rev. A2, 25-Aug-98
Target Specification