DG200A Datasheet, PDF (5/5 Pages) TEMIC Semiconductors – Monolithic Dual SPST CMOS Analog Switch

DG200A
Test Circuits
V_O is the steady state output with switch on. Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
+15 V
3V
Logic
Input _{0 V}
Switch
Input
V_S
Switch
Output
V_O
50%
90%
t_r <20 ns
t_f <20 ns
t_OFF
V_S = +5 V
3V
V+
S
D
IN
GND
V–
R_L
1 kW
V_O
C_L
35 pF
t_ON
–15 V
R_L
Figure 2. Switching Time
V_O = V_{S RL + rDS(on)}
+15 V
V+
R_g
S
D
V_O
DV_O
V_O
V_g
3V
IN
GND
V–
–15 V
C_L
1000 pF
IN_X ON
OFF
ON
DV_O = measured voltage error due to charge injection
The charge injection in coulombs is DQ = C_L x DV_O
Figure 3. Charge Injection
+15 V
C
V_S
V+
S
D
V_O
R_g = 50 W
IN
R_L
5V
GND
V– C
–15 V
Off Isolation = 20 log ^VS
V_O
Figure 4. Off Isolation
Siliconix
S-52880—Rev. B, 28-Apr-97
+15 V
C
V_S
R_g = 50 W
0V
NC
0V
V+
S₁
D₁
IN₁
S₂
D₂
IN₂
GND
V– C
50 W
V_O
R_L
–15 V
X_TALK = 20 log
V_S
V_O
C = RF bypass
Figure 5. Channel-to-Channel Crosstalk
5