U2781B Datasheet, PDF (4/10 Pages) TEMIC Semiconductors – Frequency Synthesizer

U2781B
Functional Description
The reference- and the programmable counter can be
programmed by the 3-wire bus (Clock, Data and Enable).
The Data Signal is transfered bit by bit into the shift
register during the rising edge, starting with the MSB-bit.
As soon as the enable signal is in high condition, the
content of the shift register will be taken over either into
the 15-bit reference counter latch (C = H) or into the
18-bit latch of the programmable counter (C = L)
Reference Counter (15bit shift register)
ÁÁÁLÁÁÁ_CSBÁÁÁ_RÁÁÁ₀ ÁÁÁ_RÁÁÁ₁ ÁÁÁ_RÁÁÁ₂ ÁÁÁ_RÁÁÁ₃ ÁÁÁ_R4ÁÁÁÁÁÁ_R5ÁÁÁÁÁÁ_R6ÁÁÁÁÁÁ_R7ÁÁÁÁÁÁ_R8ÁÁÁ_RÁÁÁ₉ ÁÁÁ_RÁÁÁ₁₀ ÁÁÁ_RÁÁÁ₁₁ ÁÁÁ_R1ÁÁÁ₂ ÁÁÁ_R1ÁÁÁ₃ ÁÁÁMPSSÁÁÁ_CB ÁÁÁ
C:
Control bit High
PSC: Prescaler scaling factor bit: High – 64/65
Low – 128/129
S_PSC = 64 or 128
R0 to R13: These bits are setting the reference counter S_R
S_R = R0 2⁰ + R1 2¹ + to + R12 2¹² + R13 2¹³
permitted scaling factors for S_R: 4 to 16383
Programmable Counter (18-bit shift register)
ÁÁÁ_LÁÁÁ_CSBÁÁÁÁÁÁ_S0 ÁÁÁ_SÁÁÁ₁ ÁÁÁ_S2ÁÁÁ_SÁÁÁ₃ ÁÁÁ_S4ÁÁÁ_SÁÁÁ₅ ÁÁÁ_S6ÁÁÁ_MÁÁÁ₀ ÁÁÁ_M1ÁÁÁ_MÁÁÁ₂ ÁÁÁ_M3ÁÁÁ_MÁÁÁ₄ÁÁÁ_MÁÁÁ₅ ÁÁÁ_M6ÁÁÁ_MÁÁÁ₇ ÁÁÁ_M8ÁÁÁ_MÁÁÁ₉ ÁÁÁ_MMS1ÁÁÁ_B0 ÁÁÁ
C:
Control bit Low
S0 to S6: These bits are setting the swallow counter S_S.
S_S = S0 2⁰ + S1 2¹ + to + S5 2⁵ + S6 2⁶
permitted scaling factors for S_S: 0 to 127, S_S < S_M
M0 to M10 : These bits are setting the main counter S_M.
S_M = M0 2⁰ + M1 2¹ + to + M9 2⁹ + M10 2¹⁰
permitted scaling factors for S_M: 4 to 2047
Total scaling factor S_P of the programmable counter
S_P = (S_PSC S_M) + S_S Condition: S_S < S_M
VCO Frequency
f_VCO = ((S_PSC S_M) + S_S) f_RefOsc / S_R
4 (10)
TELEFUNKEN Semiconductors
Rev. A3, 26-Nov-97