U6057B Datasheet, PDF (3/9 Pages) TEMIC Semiconductors – Receiver for Point-to-Point Multiplex Systems

U6057B
Supply Voltage 5 V
The receivers can be supplied from one stabilized, noise-
free voltage source. In this case, the series resistor and the
filter capacitor are not required. Pin V_Stab is also supplied
by the 5-V supply (see figure 4).
Structure of the Data Word
A switch information unit consists of four parts:
1. One bit for receiver synchronization
2. Information bit with ”High” = switch open
”Low” = switch closed
3. Zero bit
4. Zero bit
The data word consists of two start bits and eight
information units. For a transmitter frequency of 6.4 kHz,
the data word length is 5 ms plus the start pulse followed
by a 10-ms-long data interval. The data interval has high
potential. When the supply voltage is applied, data
transmission is constantly repeated in accordance with
this pattern.
Data Decoding
If a negative edge appears at the data input, the receiver
checks whether a start pulse or a fault is present by
measuring the duration of the pulse (a minimum time
must be observed). If there is a fault, the receiver waits for
the next negative edge.
If it recognizes a start pulse, it checks whether an
information unit with 8 bits is following and stores this in
an 8-bit overflow store. The arriving data are ignored if
there is no 8-bit string owing to a fault or a synchronism.
The receiver is synchronized by each one bit. Scanning of
the information takes place in the middle of the
information bit. In order to make scanning sufficiently
precise, the oscillator frequency of the receiver was
selected to be four times as large as that of the transmitter.
" ^{The deviation of the receiver frequency to the four-fold}
transmitter frequency may be up to 15% while still
guaranteeing reliable data cognition.
Data Check
The data read into the 8-bit overflow store is compared
with the content of the buffer. If this is identical, a 4-stage
counter is incremented by one stage. If this is not
identical, the counter is reset. The new data combination
is transferred to the buffer after each comparison
irrespective of the result.
After double or quadruple coincidence has been estab-
lished, the content of the buffer is always transferred to
the output memory.
Since the period of data transmission is 15 ms this results
in a minimum delay time of 60 ms or 30 ms for detection
of a change of the data word. Faults on the data line and
switch bouncing may lead to an extension of the delay
time.
Precondition to transfer the data word into the output
memory: Input P/S must be in high potential.
Synchronization
Proper data transfer requires a synchronization between
the internal data processing and the microcontroller’s
read-out frequency.
The U6057B provides a synchronization pulse (Pin SYN)
of t = 16 1/f_OSC which triggers the microcontroller to
read-out data in the following time window of typically
2 15 ms or 4 15 ms. The synchronization is derived
from the positive edge of the internal transfer pulse. This
pulse causes the data transfer to the output shift register
after double/quadruple data word comparison.
The microcontroller reads the output shift register after
each synchronization pulse. In practise, the time delay for
data recognition varies depending on the event of data
signal change on the data line and the status of the internal
4-stage (or 2-stage) counter. This counter is 0 after each
synchronization pulse. With a programmed quadruple
comparison the data recognition time ranges from
4 15 ms to 7 15 ms whereas it may range from
2 15 ms to 3 15 ms in the case of the programmed
double comparison.
If the system is operated with multiple change of the data-
word during the comparison time (4 15 ms or
2 15 ms), the data recognition time may last longer
than mentioned above.
Note: In master – slave operation, each IC produces its
own synchronization pulse.
Cascading (Master – Slave Operation)
Determination of master or slave is defined by the con-
necting of the Pin PP:
Master/ alone:
Slave:
PP open or PP to V_S
PP to GND
In master mode, the oscillator is connected with R_OSC and
C_OSC, and the clock output is active. In slave mode, the
oscillator is blocked and must be activated by the clock
output of the master. The master recognizes the start-bit
and decodes the first eight information bits. The slave also
TELEFUNKEN Semiconductors
3 (9)
Rev. A1, 03-Dec-97
Preliminary Information