U5020M Datasheet, PDF (3/8 Pages) TEMIC Semiconductors – Digital Window Watchdog Timer

U5020M
1000.00
100.00
t (ms)
10.00
1.00
1
C₁ = 500 pF
10
100
R₁ (kW)
Figure 3. Period t vs. R₁, @ C₁ = 500 pF
4.5 V
5.0 V
5.5 V
1000
95 10636
VDD
Reset Out
Mode
Pin 13
t_o
t₆
Pin 10
t₁
Figure 4. Power-up reset and mode switchover
Pin 12
95 10637
Supply Voltage Monitoring, Pin 10
The integrated power-on reset (POR) circuitry sets the
internal logic to a defined basic status and generates a
reset pulse at the reset output, Pin 10, during ramp-up of
the supply voltage and in the case of voltage drops of the
supply. A hysteresis in the POR threshold prevents the
circuit from oscillating. During ramp–up of the supply
voltage the reset output stays active for time, t_o, in order
to bring the microcontroller in its defined reset status (see
figure 4). Pin 10 has an open-drain output.
Switch-over Mode Time, Pin 12
The switch-over mode time enables the synchronous
operation of micro and watchdog. After the power-up
reset time the watchdog has to be switched to its
monitoring mode by the micro with a “low” signal
transmitted to the mode pin (Pin 12) within the time out
period, t₁,. If the low signal does not occur within time,
t₁, (see figure 4) the watchdog generates a reset pulse, t₆,
and the time, t₁, starts again. Micro and watchdog are
synchronized with the switchover mode time, t₁, each
time a reset pulse is generated.
Microcontroller in Active Mode
Monitoring with the “Short” Trigger
Window
After the switch-over mode the watchdog works in the
short watchdog mode and expects a trigger pulse from the
microcontroller within the defined time window, t₃,
(enable time). The watchdog generates a reset pulse
which resets the microcontroller if
D the trigger pulse duration is too long,
D the trigger pulse is within the disable time, t₂
D there is no trigger pulse
Figure 5 shows the pulse diagram with a missing trigger
pulse.
TELEFUNKEN Semiconductors
3 (8)
Rev. A3, 27-Feb-97
Preliminary Information