U4224B Datasheet, PDF (3/17 Pages) TEMIC Semiconductors – Time Code Receiver

U4224B
Q1A, Q1B
In order to achieve a high selectivity, a crystal is con-
nected between the pins Q1A and Q1B. It is used with the
serial resonance frequency of the time code transmitter
(e.g. 60 kHz WWVB, 77.5 kHz DCF or 40kHz JG2AS).
The equivalent parallel capacitor of the filter crystal is
internally compensated. The compensated value is about
0.7 pF. If the full sensitivity and selectivity is not needed,
the crystal filter can be substituted by a capacitor of 10 pF
for DCF and WWVB and 22 pF for JG2AS.
SL
AGC hold mode: SL high (V_SL = V_CC) sets normal func-
tion, SL low (V_SL = 0) disconnects the rectifier and holds
the voltage V_INT at the integrator output and also the AGC
amplifier gain.
V_CC
Q1A
Q1B
SL
94 8378
94 8382
GND
INT
REC
Rectifier output and integrator input: The capacitor C1
between REC and INT is the lowpass filter of the rectifier
and at the same time a damping element of the gain
control.
94 8374
Integrator output: The voltage V_INT is the control voltage
for the AGC. The capacitor C2 between INT and DEC
defines the time constant of the integrator. The current
through the capacitor is the input signal of the decoder.
94 8375
REC
GND
INT
GND
DEC
Decoder input: Senses the current through the integration
W ^{capacitor C2. The dynamic input resistance has a value of}
about 420k and is low compared to the impedance of
C2.
FLA, FLB
Lowpass filter: A capacitor C3 connected between FLA
and FLB supresses higher frequencies at the trigger
circuit of the decoder.
DEC
94 8376
GND
FLB
FLB
94 8377
TELEFUNKEN Semiconductors
Rev. A3, 02-Apr-96
3 (17)