U2733B-C Datasheet, PDF (3/14 Pages) TEMIC Semiconductors – Fractional-N Frequency Synthesizer for DAB Tuner

U2733B-C
For DAB mode I this phase noise weighting function is
shown in the following figure:
1,80
1,60
1,40
1,20
1,00
0,80
0,60
0,40
0,20
0,00
0 1000 2000 ³⁰⁰⁰ 4000 5000 6000 7000 8000 9000 10000
df / Hz
12477
Figure 3.
It is important to realize that this function shows zeros in
all distances from the center line which are multiples of
the carrier spacing. The technique of concentrating the
phase noise in the positions of such zeros is protected by
a patent.
In this circuit the phase detector is operated at a frequency
which is four times the desired frequency raster spacing
(e.g., 16 kHz in case of DAB) and the well known
fractional-N technique is used to synthesize the raster. As
a result of this technique in the VCO’s frequency
spectrum spurious occur not only in multiples of the phase
detectors input comparison frequency (64 kHz) but also
in multiples of the raster frequency (16 kHz). As
described above for all DAB modes these spurious are
placed in spectral positions where the phase noise
weighting function is zero. Therefore no measures are
necessary to suppress these lines.
Reference Divider
Four different scaling factors SF_ref of the reference
divider can be selected by means of the bits ‘RD1’ and
‘RD2’ in the I²C bus instruction code: 256, 280, 288, and
384. Starting from a reference oscillator frequency of
16.384 MHz/ 17.92 MHz/ 18.432 MHz/ 24.576 MHz
these scaling factors provide a frequency raster of
64 kHz. By changing the division ratio of the main
divider from N to N+1 in an appropriate way
(fractional-N technique) this frequency raster is
interpolated to deliver a frequency spacing of 16 kHz
according to the DAB specification. So effectively the
reference divide factors 1024, 1120, 1152 and 1536 can
be selected. By setting of the I²C bus bit ‘T’ a test signal
representing the divided input signal can be monitored at
the switching output SWC.
Main Divider
The main divider consists of a fully programmable 13-bit
divider which defines a division ratio N. The applied
division ratio is either N or N+1 according to the control
of a special control unit. On average the scaling factors
SF = N+k/ 4 can be selected where k = 0, 1, 2, 3. In this
way VCO frequencies
f_VCO = 4 (N+k/4) f_ref/(4 SF_ref)
can be synthesized starting from a reference frequency
f_ref.. If we define SF_eff = 4 N+k and SF_{ref, eff} = 4 SF_ref
we end up with
f_VCO = SF_eff f_ref/SF_ref,eff,
where SF_eff is defined by 15 bits. In the following this
circuit is described in terms of SF_eff and SF_ref,eff. SF_eff has
to be programmed via the I²C bus interface. An effective
scaling factor from 2048 up to 32767 can be selected. By
setting of the I²C bus bit ‘T’ a test signal representing the
divided input signal can be monitored at the switching
output SWF.
When the supply voltage is switched on both the reference
divider and the programmable divider are kept in
RESET state till a complete scaling factor is written onto
the chip. Changes in the setting of the programmable
divider become active when the corresponding I²C bus
transmission is completed. By an internal synchro-
nization procedure is ensured that such changes don’t
become active while the charge pump is sourcing or
sinking current at its output pin. This behavior allows a
smooth tuning of the output frequency without disturbing
the controlled VCO’s frequency spectrum.
Phase Comparator and Charge Pump
The tri-state phase detector causes the charge pump to
source or to sink current at the output pin PD depending
on the phase relation of its input signals which are
provided by the reference and the main divider
respectively. Four different values of this current can be
selected by means of the I²C bus bits ‘I50’ and ‘I100’. By
use of this option for example changes of the loop
characteristics due to the variation of the VCO gain as a
function of the tuning voltage can be reduced. The charge
pump current can be switched off using the I²C bus bit
‘TRI’. A change in the setting of the charge pump current
becomes active when the corresponding I²C bus
transmission is completed. As described for the setting of
the scaling factor of the programmable divider an internal
synchronization procedure ensures that such changes
don’t become active while the charge pump is sourcing or
sinking current at its output pin. This behavior allows a
change in the charge pump current without disturbing the
controlled VCO’s frequency spectrum.
TELEFUNKEN Semiconductors
3 (14)
Rev. A1, 21-Aug-96
Preliminary Information