U2352B Datasheet, PDF (3/8 Pages) TEMIC Semiconductors – PWM Power Control for DC Loads

U2352B
Pin Description
Osc 1
V_{Contr 2}
I_Set 3
S₂OUT 4
8 _VS
7 Output
6 GND
5 S₂IN
95 9701
Pin Symbol
Function
1
Osc Oscillator
2
V_Contr Control voltage input
3
I_Set Setpoint value current
monitoring
4
S₂OUT Output, current switch S₂
5
S₂IN Input, current switch S₂
6
GND Ground
7
Output Output
8
V_S Supply voltage
Supply, Pin 8
Internal voltage limitation in the U2352B allows a simple
supply via a series resistor R₁. This enables operation of
the circuit under different operating voltages. Supply
voltage between Pin 8 (V_S) and Pin 6 (GND) builds up via
R₁ and is smoothed by C₁.
+ ^{* The series resistor R1 is calculated as follows:}
R_1max
V_Bmin V_Smax
I_tot
where
V_Bmin = Minimum operating voltage
V_Smax = Maximum supply voltage
I_tot = I_Smax + I_X
I_Smax = Maximum current consumption of the IS
I_X = Current consumption of the external elements
Various thresholds are derived from an internal reference
voltage source.
Voltage Monitoring
During build-up and reduction of the operating voltage,
uncontrolled output pulses with excessively low ampli-
tude are suppressed by the internal monitoring circuit. All
latches are reset and the output of the load current detec-
tion Pin 4 is switched to ground.
Chip Temperature Monitoring
U2352B has integrated chip temperature monitoring
which switches off the output stage when a temperature
of approximately 140°C is reached. The device is not
enabled again until cooling has taken place and the supply
voltage has been switched off and then back on again.
Pulse Width Control, Pins 1 and 2
At the frequency-determining capacitor, C_osc, at Pin 1,
switching over of two internal current sources gives rise
to a triangular voltage which comparator, K₁, compares
with the control voltage at Pin 2. If the voltage, V₁, is
more negative than the control voltage V₂, the output
stage is switched on via the output stage logic. When C_osc
is charged, the whole process then runs in reverse order
(see figure 3).
Load Current Monitoring, Pins 3, 4, 5
Load current can be measured with the aid of an external
shunt resistor, but this is only appropriate for decreased
loads due to additional power loss and component size
and costs. This involves the shunt voltage being fed
directly to Pin 4 via a protective resistor (see figure 5).
In order to save component costs and additional power
loss, the integrated load current monitoring allows the
load current to be directly measured via the voltage drop
at the on-state resistance, R_DS(on), of the FET, without an
additional shunt resistor. The drain voltage of the FET is
supplied via an external protective resistor to Pin 5.
During the off-state of the FET, a diode clamp circuit
protects the detection input, Pin 5. In the on state, the load
current flowing through the FET generates a
corresponding voltage drop at its R_DS(on), which is in turn
converted into a current at Pin 5 by the protective resistor.
This current reaches the integration element at Pin 4 via
the switch S₂, which is only closed in the on-state of the
FET. If the voltage at Pin 4 exceeds the setpoint value set
at Pin 3, as a result of a high load current, the shutdown
latch is set and the output stage is blocked. To enable the
circuit again, it is necessary to switch the operating
voltage off and then back on again.
Switch-off behavior is adjusted with the resistors at Pin 4
and Pin 5 and also with the capacitor at Pin 4.
TELEFUNKEN Semiconductors
3 (8)
Rev. A1, 29-May-96