U208B Datasheet, PDF (2/7 Pages) TEMIC Semiconductors – Open Loop Phase Control Circuit

U208B
Description
Mains Supply
The U208B is fitted with voltage limiting and can there-
ă ^{fore be supplied directly from the mains. The supply}
voltage between Pin 1 (+ pol/ ) and Pin 2 builds up
across D₁ and R₁ and is smoothed by C₁. The value of the
series resistance can be approximated using figure 1:
+ R₁
V_M–V_S
2 I_S
Further information regarding the design of the mains
supply can be found in the data sheets in the appendix.
Operation using an externally stabilized DC voltage is not
recommended.
If the supply cannot be taken directly from the mains
because the power dissipation in R₁ would be too large,
then the circuit shown in the following figure 2 should be
employed.
~
24 V~
1
2
3
4
5
R₁
C₁
95 10362
Figure 2. Supply voltage for high current requirements
Phase Control
The function of the phase control is largely identical to
that of the well known component TEA1007. The phase
angle of the trigger pulse is derived by comparing the
ramp voltage, which is mains synchronized by the voltage
detector, with the nominal value predetermined at the
control input Pin 6. The slope of the ramp is determined
by C₂ and its charging current. The charging current can
be varied using R₂ on Pin 4. The maximum phase angle
a_max can also be adjusted using R₂.
When the potential on Pin 5 reaches the given value of
Pin 6, then a trigger pulse is generated whose width t_p is
determined by the value of C₂ (the value of C₂ and hence
the pulse width can be evaluated by assuming 8 ms/nF).
The current sensor on Pin 8 ensures that, for operation
with inductive loads, no pulse will be generated in a new
half cycle as long as the current from the previous half
cycle is still flowing in the opposite direction to the sup-
ply voltage at that instant. This makes sure that ”Gaps” in
the load current are prevented. The control signal on Pin
6 can be in the range 0 V to –7 V (reference point Pin 1).
If V_pin6 = –7 V then the phase angle is at maximum = a_max
i.e., the current flow angle is a minimum. The minimum
phase angle a_min is when V_pin6 = V_pin1.
Voltage Monitoring
As the voltage is built up, uncontrolled output pulses are
avoided by internal voltage surveillance. At the same
time, all of the latches in the circuit are reset. Used with
a switching hysteresis of 300 mV, this system guarantees
defined start–up behavior each time the supply voltage is
switched on ,or after short interruptions of the mains
supply.
Pulse Output Stage
The pulse output stage is short circuit protected and can
typically deliver currents of 125 mA. For the design of
smaller triggering currents, the function I_GT = f (R_GT) has
been given in the data sheets in the appendix. In contrast
to the TEA1007, the pulse output stage of the U 208 B has
no gate bypass resistor.
Automatic Retriggering
The automatic retriggering prevents half cycles without
current flow, even if the triacs is turned off earlier e.g. due
to a collector which is not exactly centered (brush lifter)
or in the event of unsuccessful triggering. If it is neces-
sary, another triggering pulse is generated after a time
lapse of t_pp = 4.5 t_p and this is repeated until either the
triac fires or the half cycle finishes.
2 (7)
TELEFUNKEN Semiconductors
Rev. A1, 28-May-96