TSC87251G1A Datasheet, PDF (18/52 Pages) TEMIC Semiconductors – Extended 8-bit Microcontroller with Serial Communication

TSC87251G1A
Table 21. Summary of Increment and Decrement Instructions
Increment
Increment
Decrement
Decrement
INC <dest>
INC <dest>, <src>
DEC <dest>
DEC <dest>, <src>
Mnemonic <dest>, <src>⁽¹⁾
Comments
dest opnd ← dest opnd + 1
dest opnd ← dest opnd + src opnd
dest opnd ← dest opnd – 1
dest opnd ← dest opnd – src opnd
Binary Mode
Source Mode
Bytes States Bytes States
INC
DEC
INC
DEC
INC
DEC
INC
A
Rn
dir8
@Ri
Rm, #short
WRj, #short
DRk, #short
DRk, #short
DPTR
ACC by 1
Register by 1
Direct address (on–chip RAM or SFR) by 1
Indirect address by 1
Byte register by 1, 2, or 4
Word register by 1, 2, or 4
Double word register by 1, 2, or 4
Double word register by 1, 2, or 4
Data pointer by 1
1
1
1
1
1
1
2
2
2
2⁽²⁾
2
2⁽²⁾
1
3
2
4
3
2
2
1
3
2
2
1
3
4
2
3
3
5
2
4
1
1
1
1
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 22. Summary of Compare Instructions
Compare
CMP <dest>, <src>
dest opnd – src opnd
Mnemonic <dest>, <src>⁽¹⁾
Comments
Binary Mode
Bytes States
Source Mode
Bytes States
Rmd, Rms
Register with register
3
2
2
1
WRjd, WRjs
Word register with word register
3
3
2
2
DRkd, DRks
Dword register with dword register
3
5
2
4
Rm, #data
Register with immediate data
4
3
3
2
WRj, #data16
Word register with immediate 16-bit data
5
4
4
3
DRk, #0data16
Dword register with zero-extended 16-bit immediate
5
6
4
5
data
CMP
DRk, #1data16
Dword register with one-extended 16-bit immediate data
5
6
4
5
Rm, dir8
Direct address (on–chip RAM or SFR) with byte register
4
3⁽¹⁾
3
2⁽¹⁾
WRj, dir8
Rm, dir16
WRj, dir16
Rm, @WRj
Rm, @DRk
Direct address (on–chip RAM or SFR) with word
register
Direct address (64K) with byte register
Direct address (64K) with word register
Indirect address (64K) with byte register
Indirect address (16M) with byte register
4
4
3
3
5
3⁽²⁾
4
2⁽²⁾
5
4⁽³⁾
4
3⁽³⁾
4
3⁽²⁾
3
2⁽²⁾
4
4⁽²⁾
3
3⁽²⁾
Notes:
1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
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Rev. A – September 21, 1998