CIE03 Datasheet, PDF (2/11 Pages) TEMEX – Digital pulse compression module

Digital pulse compression module
CI E03
Technical description
CI E03 functional bloc diagram is featured on Fig. 2.
RF OUT B (J5)
DA C
250 MS PS
16 bits
RF OUT A (J4)
RE FCLK (J6)
RF INA (J2)
RF INB (J3)
DA C
250 MS PS
16 bits
Os c
ADC
250 MS PS
12 bits
ADC
250 MS PS
12 bits
PLL /
VCO
FP GA
XC 5VSX 35T
Po wer
Co ntrol
CP LD
Superv ision
BIT E
IF
(J1 )
FPGA config (SPI )
JTA G
VA NA (x2)
US ER (x15)
US ER (x4)
BO ARD_OK
Sta tus (x3)
N_ RST
CLKEXT _EN
VCFG
N_ BOA RD_PD
VINMA IN
VINVCO
Fig. 2 : CI E03 functional bloc diagram
This module is specifically designed to upgrade existing SAW based pulse compression subsystems. Plugged on a
specific carrier board, this module may upgrade many existing expanders and/or compressors. With a low size
and low profile, it may be embedded in small form factors.
This module is able to process on-the-fly 2 independent and concurrent channels. Each channel may be an
expander or a compressor. The two independent channels are processed in a single FPGA, but each of them uses
dedicated resources.
The internal clock generator is self-sufficient but may also be locked on an external clock. An external clock is
required for expander channels, but is optional for compressor channels.
As the two channels uses the same ADC, same DAC component types and the same reference clock, the phase
difference will be close to 0, and will be very stable inside the operating range. There is no need to use phase
shifters to adjust phase difference.
16 different waveforms, each of them with different specification, may be stored for each expander channel.
The active waveform is selected with 4 user inputs on J1 connector. Expander channel waveforms allows for
Doppler pre-correction, e.g. there may be 2 waveforms with different specifications, each of them with 8
different Doppler pre-corrections ranging from negative values to positive values.
FPGA firmware resides inside a flash PROM located on the carrier board, thus CI E03 has not to be application
dependant; the same CI E03 board may be used without any modification or firmware upgrade for different
applications. Firmware is automatically loaded in the FPGA at startup.
CI E03 module continuously monitors its internal temperature, powers off FPGA and some other components
and deasserts TEMP_OK signal on J1 connector if temperature exceeds a secure maximum threshold.
CI E03 module is provided with FPGA firmware to be loaded on the carrier flash memory. Functions, and
channels specifications (time dispersion, compressed pulse width, side lobes level,…) should be provided by
customer; Rakon will customize the FPGA program to fulfill customer requirements.
Expander channel bloc diagram is featured in Fig. 3. After each trigger pulse, a chirp defined by the samples set
selected by EXP_SELECT_x (user signals) is generated, and presented to the DAC input to be translated into an
analog signal. When the control input state changes, another waveform samples set is selected, and will be
active for the next trigger pulse.
For better compatibility with old SAW based subsystems, an adjustable additional delay may be inserted.
March 15^th, 2013
CI E03 Revision A3
2 / 11
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