TC18C43 Datasheet, PDF (2/7 Pages) TelCom Semiconductor, Inc – BiCMOS CURRENT MODE PWM CONTROLLERS

TC18C43
TC28C43
TC38C43
BiCMOS CURRENT MODE
PWM CONTROLLERS
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage ............................................................18V
Maximum Chip Temperature ................................... 150°C
Storage Temperature ............................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
Package Thermal Resistance
CerDip R_θJ-A ................................................ 150°C/W
CerDip R_θJ-C .................................................. 55°C/W
PDIP R_θJ-A ................................................... 125°C/W
PDIP R_θJ-C ..................................................... 45°C/W
SOIC R_θJ-A ................................................... 250°C/W
SOIC R_θJ-C ..................................................... 75°C/W
Operating Temperature
18C4x ...................................... – 55C° ≤ T_A ≤ +125°C
28C4x ........................................ – 40C° ≤ T_A ≤ +85°C
38C4x ............................................. 0C° ≤ T_A ≤ +70°C
ELECTRICAL CHARACTERISTICS unless otherwise stated, these specifications apply over specific
temperature range. V_IN = V_DD = 15V; R_T = 71 kΩ; C_T = 150 pF.
TC18C43
TC28C43
TC38C43
Parameter
Test Conditions
Min Typ Max Min Typ Max Units
Reference Section
Output Voltage
Line Regulation
Load Regulation
Temp Stability
T_A = 25°C, I_O = 1mA
9.5V ≤ V_IN ≤ 15V, I_O = 1mA
1mA ≤ l_O ≤ 11mA
(Note 1)
Output Noise Voltage
Long Term Stability
Output Short Circuit
10Hz ≤ f ≤ 10 kHz,T_A = 25°C (Note 1)
T_A = 125°C, 1000 Hrs. (Note 1)
Oscillator Section
Initial Accuracy
Voltage Stability
Temp Stability
Clock Ramp Reset
Amplitude
Maximum Freq
T_A = 25°C (Note 4)
9.5V ≤ V_IN ≤ 15V
T_MIN ≤ T_A ≤ T_MAX (Note 1); Figure 2
R_T/C_T Pin at 4V
R_T/C_T Pin Peak to Peak
Note 1
Error Amp Section
Input Offset Voltage
Input Bias Current
V_(CMPTR) = 2.5V
(Note 1)
A_VOL
2V ≤ V_O ≤ 4V
Gain Bandwidth Product (Note 1)
PSRR
Output Sink Current
Output Source Current
V_OUT High
V_OUT Low
Rise Response
9.5V ≤ V_IN ≤ 15V
V_FB = 2.7V, V_(CMPTR) = 1.1V (Note 1)
V_FB = 2.3V, V_(CMPTR) = 5V (Note 1)
V_FB = 2.3V, R_L = 10k to Ground
V_FB = 2.7V, R_L = 10k to V_REF
Note 1
Fall Response
Note 1
Current Sense Section
Gain Ratio
Notes 2 & 3
Maximum Input Signal
PSRR
Input Bias Current
V_(CMPTR) = 5V (Note 2)
9.5V ≤ V_IN ≤ 15V (Notes 1, 2 & 5)
Note 1
Delay to Output
V₍I_SENSE) = 1V (Note 1); Figure 3
4.9 5
5.1
— ±3 ±10
— ±5 ±15
— ±0.25 ±0.5
— 100 —
— ±0.5 —
-20 -50 -100
4.90 5
—
±3
—
±3
— ±0.25
— 100
— ±0.5
-30 -50
5.10
±10
±10
±0.5
—
—
-100
V
mV
mV
mV/°C
µV(rms)
%
mA
90 100 110 93.8 100 106.5
— ±0.2 ±0.3 — ±0.2 ±0.3
— ±0.01 ±0.05 — ±0.01 ±0.03
2.25 2.5 2.75 2.25 2.5 2.75
2.45 2.65 2.85 2.45 2.65 2.85
1
—
—
1
—
—
kHz
%
%/°C
mA
V
MHz
— ±15 ±50 — ±15 ±50
mV
— ±0.3 ±2
— ±0.3 ±2
nA
70 90
—
70
90
—
dB
650 750 — 650 750
—
kHz
80 100 —
80 100
—
dB
1.2 1.5 — 1.5 1.7
—
mA
3
3.4 —
3.9 4.2
—
mA
5.65
6 6.5 5.65 6
6.5
V
0.1
0.7 1.1
0.1 0.7
1.1
V
—
5
7
—
5
7
µsec
—
3
5
—
3
5
µsec
2.8
2.9 3.1
2.8 2.9
3.1
V/V
0.85 0.95 1.05 0.85 0.95 1.05
V
70
80 —
70
80
—
dB
— ±0.3 ±2
— ±0.3 ±2
nA
—
140 160
— 140 150 nsec
4-94
TELCOM SEMICONDUCTOR, INC.