TMS29F040_08 Datasheet, PDF (17/37 Pages) Texas Instruments – Erase-Suspend/Erase-Resume Operation

TMS29F040
524ā288 BY 8ĆBIT
FLASH MEMORY
SMJS820C − APRIL 1996 − REVISED JUNE 1998
timing requirements controlled by E (see Figure 5)
tAVAV
tEHEH1
tEHEH2
tEHEH3
Cycle time, write
Cycle time, programming operation
Cycle time, sector-erase operation
(see Note 10)
Cycle time, chip-erase operation
(see Note 11)
ALTERNATE
SYMBOL
tc(W)
’29F040-60
MIN TYP MAX
60
18
’29F040-70
MIN TYP MAX
70
18
’29F040-90
MIN TYP MAX
90
18
UNIT
ns
µs
1
30
1 30
1 30 s
8 120
8 120
8 120 s
tEHDX
tEHWH
tELAX
tELEH
tEHEL
tGHEL
tAVE_L
tDVEH
tWLEL
Hold time, data
Hold time, W
Hold time, address
Pulse duration, E low
Pulse duration, E high
Recovery time, read before write
Setup time, address
Setup time, data
Setup time, W
th(D)
0
th(W)
0
th(A)
40
tw(EL)
30
tw(EH)
20
trec(R)
0
tsu(A)
0
tsu(D)
30
tsu(W)
0
0
0
ns
0
0
ns
45
45
ns
35
45
ns
20
20
ns
0
0
ns
0
0
ns
30
45
ns
0
0
ns
ALTERNATE
SYMBOL
tAVAV
Cycle time, write
tc(W)
tEHEH1 Cycle time, programming operation
tEHEH2 Cycle time, sector-erase operation (see Note 10)
tEHEH3 Cycle time, chip-erase operation (see Note 11)
tEHDX Hold time, data
th(D)
tEHWH Hold time, W
th(W)
tELAX Hold time, address
th(A)
tELEH Pulse duration, E low
tw(EL)
tEHEL Pulse duration, E high
tw(EH)
tGHEL Recovery time, read before write
trec(R)
tAVE_L Setup time, address
tsu(A)
tDVEH Setup time, data
tsu(D)
tWLEL Setup time, W
tsu(W)
NOTES: 10. Timing diagram of E-controlled sector-erase operation not enclosed.
11. Timing diagram of E-controlled chip-erase operation not enclosed.
’29F040-10
MIN TYP MAX
100
18
1 30
8 120
0
0
45
45
20
0
0
45
0
’29F040-12
MIN TYP MAX
120
18
1 30
8 120
0
0
50
50
20
0
0
50
0
UNIT
ns
µs
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
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