C0402C0G1C330JT Datasheet, PDF (6/34 Pages) TDK Electronics – MULTILAYER CERAMIC CHIP CAPACITORS

(continued)
No.
Item
7 Temperature
Characteristics
of Capacitance
(Class1)
8 Temperature
Characteristics
of Capacitance
(Class2)
9 Robustness of
Terminations
10 Bending
Performance
T.C.
Temperature Coefficient
(ppm/°C)
CH
0 ± 60
C0G
0 ± 30
Capacitance drift
Within ± 0.2% or ±0.05pF,
whichever larger.
Capacitance Change (%)
No voltage With voltage
applied
applied
J B : ±10
X5R : ±15
X6S : ±22
X7R : ±15
X7S : ±22
X7T : +22
-33
J B : + 10
− 30
: + 10
− 50
: + 10
− 60
: ——
——
Test or inspection method
Temperature coefficient shall be
calculated based on values at 25°C and
85°C temperature.
Measuring temperature below 20°C shall
be -10°C and -25°C.
Capacitance shall be measured by the
steps shown in the following table after
thermal equilibrium is obtained for each
step.
∆C be calculated ref. STEP3 reading
Step
Temperature(°C)
1
Reference temp. ± 2
2 Min. operating temp. ± 2
3
Reference temp. ± 2
4 Max. operating temp. ± 2
Measuring voltage: 0.1, 0.2, 0.5, 1.0Vrms.
For information which product has which
applied voltage, please contact with our
sales representative.
No sign of termination coming off,
breakage of ceramic, or other
abnormal signs.
Reflow solder the capacitors on a
P.C.Board shown in Appendix 1a or
Appendix 1b and apply a pushing force
of 2N (C0603, C1005) or 5N (C1608,
C2012, C3216, C3225, C4532, C5750)
with 10±1s.
(Not applicable to C0402.)
Pushing force
No mechanical damage.
P.C.Board
Capacitor
Reflow solder the capacitors on a
P.C.Board shown in Appendix 2a or
Appendix 2b and bend it for 1mm.
20
50
F
R230
1
45
45
(Unit : mm)
—5—