73K222AU Datasheet, PDF (32/40 Pages) TDK Electronics – Single-Chip Modem Modem with UART

73K222AU
Single-Chip Modem
with UART
ELECTRICAL SPECIFICATIONS (continued)
PARALLEL BUS INTERFACE (See Figure 5) The following times are for CI = 100 pF.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
Dual-Port Mode Single-Port Mode
RC
Read Cycle = TAD + TRC
240
340
ns
TDIW DISTR Width
30
30
ns
TDDD Delay DISTR to Data (read time)
45
45
ns
THZ** DISTR to Floating Data Delay
50
40
ns
TRA Address Hold after DISTR
20
5
ns
TRCS Chip select hold after DISTR
20
20
ns
TAR* DISTR Delay after Address
22
15
ns
TCSR DISTR Delay after Chip Select
20
20
ns
WC
Write Cycle = TAW + TDOW + TWC
140
140
ns
TDOW DOSTR Width
40
40
ns
TDS Data Setup
15
25
ns
TDH** Data Hold
5
5
ns
TWA Address Hold after DOSTR
20
5
ns
TWCS Chip select hold after DOSTR
20
20
ns
TAW* DOSTR delay after Address
0
15
ns
DOSTR delay after Chip Select
20
20
ns
TADS Address Strobe Width
15
ns
TAS Address Setup Time
10
ns
TAH Address Hold Time
0
ns
TCS Chip Select Setup Time
10
ns
TCH Chip Select Hold Time
0
ns
TRC Read Cycle Delay
40
40
ns
TWC Write Cycle Delay
40
40
ns
TAD Address to Read Data
110
110
ns
* TAR and TAW are referenced from the falling edge of either CS@ or DISTR or DOSTR, whichever is later.
** THZ and TDH are referenced from the rising edge of CS@ or DISTR or DOSTR, whichever is earlier.
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