TCS3471 Datasheet, PDF (9/22 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – COLOR LIGHT-TO-DIGITAL CONVERTER

TCS3471
COLOR LIGHT-TO-DIGITAL CONVERTER
TAOS115 − MARCH 2011
Interrupts
The interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for
light intensity values outside of a user-defined range. While the interrupt function is always enabled and it’s
status is available in the status register (0x13), the output of the interrupt state can be enabled using the RGBC
interrupt enable (AIEN) field in the enable register (0x00).
Two 16-bit interrupt threshold registers allow the user to set limits below and above a desired light level range.
An interrupt can be generated when the RGBC Clear data (CDATA) falls outside of the desired light level
range, as determined by the values in the RGBC interrupt low threshold registers (AILTx) and RGBC interrupt
high threshold registers (AIHTx). It is important to note that the low threshold value must be less than the high
threshold value for proper operation.
To further control when an interrupt occurs, the device provides a persistence filter. The persistence filter allows
the user to specify the number of consecutive out-of-range RGBC occurrences before an interrupt is generated.
The persistence register (0x0C) allows the user to set the persistence (APERS) value. See the persistence
register for details on the persistence filter values. Once the persistence filter generates an interrupt, it will
continue until a special function interrupt clear command is received (see command register).
AIHTH(r 07), AIHTL(r 06)
PPERS(r 0x0C, b3:0)
Clear
Clear
ADC
Clear
Data
Upper Limit
Lower Limit
RGBC Persistence
AILTH(r 05), AILTL(r 04)
Figure 8. Programmable Interrupt
State Diagram
Figure 9 shows a more detailed flow for the state machine. The device starts in the sleep mode. The PON bit
is written to enable the device. A 2.4-ms delay will occur before entering the start state. If the WEN bit is set,
the state machine will cycle through the wait state. If the WLONG bit is set, the wait cycles are extended by 12×
over normal operation. When the wait counter terminates, the state machine will step to the RGBC state.
The AEN should always be set. In this case, a minimum of 1 integration time step should be programmed. The
RGBC state machine will continue until it reaches the terminal count, at which point the data will be latched in
the RGBC register and the interrupt set, if enabled.
WLONG = 0
1 to 256 steps
Step: 2.4 ms
Time: 2.4 ms − 614 ms
Minimum − 2.4 ms
WLONG = 1
1 to 256 steps
Step: 29 ms
Time: 29 ms − 7.4 s
Minimum − 29 ms
Sleep
PON = 1
PON = 0
1 to 256steps
Step: 2.4 ms
Time: 2.4 ms − 614 ms
Start
Wait
Check
WEN = 1
Wait
ALS
ALS
Check
AEN = 1
ALS
Delay
Time: 2.4 ms
Figure 9. Expanded State Diagram
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