HD3SS6126EVM Datasheet, PDF (5/12 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – HD3SS6126EVM Device Reference Design

Preliminary
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0603
NC,100u
C100
U20
VBUS_PWR ¹
2
USB2_D_N
3
USB2_D_P
GND ⁴
5
USB3_RX_N
USB3_RX_P ⁶
GND1 ⁷
8
USB3_TX_N
USB3_TX_P ⁹
SHIELD_GND1 ¹⁰
11
SHIELD_GND2
LP3
3P3V_VCC
LP1
LP4
LP2
R1
0R
Remove 2 cap since
there are only 4 VCC pins.
C1
0.1 µF
C2
0.1 µF
C3
0.1 µF
C4
0.1 µF
Reference Schematics
Note: The differential characteristic
impedance for the differential pairs is
recommended to be 90 Ω; Single-end
characteristic impedance 50 Ω.
C8
NC, 10 µF
R20
0R
Dev_HSA_DM
F1
11
22
Fuse
Dev_HSA_DP
Dev_SSA_RX(n)
PAGE3 OE#
Dev_SSA_RX(p)
Dev_SSA_TX(n)
Dev_SSA_TX(p)
PAGE3 OE#
VBUS PAGE3
USBID_A
PAGE3 HS_SEL
Dev_SSA_TX(p)
Dev_SSA_TX(n)
Dev_SSA_RX(p)
Dev_SSA_RX(n)
Dev_HSA_DM
Dev_HSA_DP
PAGE3 SS_SEL
U1
42
2 ^HSA1(n)
HSA1(p)
3
41
SEL1
HS_OE1#
38
HSC1(n) ₃₇
HSC1(p)
HSB1(n)
HSB1(p)
36
35
USB2_ID
USB1_ID
HD3SS612x Mux switch
11
12
15
16
SSA0(p)
SSA0(n)
SSA1(p)
SSA1(n)
7
8 ^HSA(n)
HSA(p)
9
6
SEL0
HS_OE0#
SSB0(p)
SSB0(n)
SSB1(p)
SSB1(n)
SSC0(p)
29
28
27
26
25
24
SSC0(n) ₂₃
SSC1(p) ₂₂
SSC1(n)
HSC0(n)
HSC0(p)
HSB0(n)
HSB0(p)
34
33
32
31
Host_SSB_TX(p)
Host_SSB_TX(n)
Host_SSB_RX(p)
Host_SSB_RX(n)
Host_SSC_TX(p)
Host_SSC_TX(n)
Host_SSC_RX(p)
Host_SSC_RX(n)
Host_HSC_DM
Host_HSC_DP
Host_HSB_DM
Host_HSB_DP
USB1_Dev_SSB_RX(p)
USB1_Dev_SSB_RX(n)
USB1_Dev_SSB_TX(p)
USB1_Dev_SSB_TX(n)
USB2_Dev_SSC_RX(p)
USB2_Dev_SSC_RX(n)
USB2_Dev_SSC_TX(p)
USB2_Dev_SSC_TX(n)
USB2_HSC_DM
USB2_HSC_DP
USB1_HSB_DM
USB1_HSB_DP
PAGE4
PAGE4
PAGE4
PAGE4
PAGE4
PAGE4
PAGE4
PAGE4
PAGE4
PAGE4
PAGE4
PAGE4
USB3_STANDARD_TYPE_A_RECEPTACLE
Note: Standard-A Receptacle Tx and
Rx are defined from the host
perspective
Thermal
Pad, not
an actual
pin
J5
SilkScreen: Default no shunts on J5
USBID_A
R109
4.98 kΩ
SLAU541 – October 2013
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HD3SS6126EVM Device Reference Design 5