PCM1795 Datasheet, PDF (47/63 Pages) Texas Instruments – 32-Bit, 192-kHz Sampling, Advanced Segment, Stereo Audio Digital-to-Analog Converter

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DBCK
t = 1/(64 ´ 44.1 kHz)
PCM1795
SLES248A – MAY 2009 – REVISED MARCH 2015
DSDL,
DSDR
D0
D1
D2
D3
D4
Figure 64. Normal Data Output Form From DSD Decoder
DBCK
DSDL,
DSDR
t_(BCH)
t_(BCL)
t_(BCY)
t_(DS)
t_(DH)
Figure 65. Timing for DSD Audio Interface
1.4 V
1.4 V
Table 36. Timing Characteristics for Figure 65
t_(BCY)
t_(BCH)
t_(BCL)
t_(DS)
t_(DH)
DBCK pulse cycle time
DBCK high-level time
DBCK low-level time
DSDL, DSDR setup time
DSDL, DSDR hold time
MIN
85 ⁽¹⁾
30
30
10
10
(1) 2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified as a sampling rate of DSD.
MAX
UNIT
ns
ns
ns
ns
ns
8.2.3.2.4 DSD Mode Configuration and Function Controls
8.2.3.2.4.1 Configuration for the DSD Interface Mode
The DSD interface mode is selected by setting DSD = 1 (register 20, B5).
Table 37. DSD Mode Register Map
REGISTER B15 B14 B13 B12 B11 B10 B9
Register 16 R/W
0
0
1
0
0
0
Register 17 R/W
0
0
1
0
0
0
Register 18 R/W
0
0
1
0
0
1
Register 19 R/W
0
0
1
0
0
1
Register 20 R/W
0
0
1
0
1
0
Register 21
R
0
0
1
0
1
0
Register 22
R
0
0
1
0
1
1
B8
B7
B6
B5
0
X ⁽¹⁾
X
X
1
X
X
X
0
X
X
X
1
REV
X
X
0
X SRST 1
1
X
X
X
0
X
X
X
(1) Function is disabled. No operation even if data bit is set.
B4
X
X
X
OPE
X
X
X
B3
B2
X
X
X
X
DMF1 DMF0
X
X
MONO CHSL
X
DZ1
X
X
B1
X
X
X
X
OS1
DZ0
ZFGR
B0
X
X
X
X
OS0
X
ZFGL
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