TMS416800 Datasheet, PDF (3/25 Pages) Texas Instruments – 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS

TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
RAS-only refresh
TMS416800
A refresh operation must be performed at least once every 64 ms to retain data. The refresh operation can be
achieved by strobing each of the 4 096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh.
TMS417800
A refresh operation must be performed at least once every 32 ms to retain data. The refresh operation can be
achieved by strobing each of the 2 048 rows (A0 – A10). A normal read or write cycle refreshes all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. The hidden refresh operation
is accomplished by holding CAS at V_IL after a read or write operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address
is generated internally.
CAS-before-RAS ( CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter t_CSR) and then holding it low
after RAS falls (see parameter t_CHR). For successive CBR refresh cycles, CAS can remain low while cycling
RAS. The external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full V_CC level. The eight initialization cycles must include at least one refresh
( RAS-only or CBR ) cycle.
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