AFE7222_14 Datasheet, PDF (27/107 Pages) Texas Instruments – Analog Front End Wideband Mixed-Signal Transceiver

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AFE7222
AFE7225
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Register Name – CONFIG11 – Address 0x110 Default = 0x00 (Optionally Synced )
<7>
<6>
<5>
<4>
<3>
TX_QMC_OFFSETA(4:0)
<2>
<1>
<0>
TX_QMC_GAINA(2:0)
TX_QMC_OFFSETA(4:0) – Lower 5 bits of DAC A Offset Correction .
TX_QMC_GAINA(2:0) – Lower 3 bits of the 11 bit QMC Gain word for DAC A. The upper 8 bits are in
CONFIG12 register.The full 11 bit TX_QMC_GAINA(10:0) word is formatted as UNSIGNED with a range
or 0 to 1.9990 . The implied decimal point for the multiplication is between bits (9) and (10).
Register Name – CONFIG12 – Address 0x111 Default = 0x00 (Synced )
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_GAINA(10:3)
TX_QMC_GAINA(10:3) –Upper 8 bits if the 11 bit QMC Gain word for DAC A.
Register Name – CONFIG13 – Address 0x112 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_OFFSETB(12:5)
TX_QMC_OFFSETB(12:5) –Upper 8 bits of DAC B Offset Correction. The lower 5 bits are in CONFIG14
Register.
Register Name – CONFIG14 – Address 0x113 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
TX_QMC_OFFSETB(4:0)
<2>
<1>
<0>
TX_QMC_GAINB(2:0)
TX_QMC_OFFSETB(4:0) – Lower 5 bits of DAC B Offset Correction .
TX_QMC_GAINB(2:0) – Lower 3 bits of the 11 bit QMC Gain word for DAC B. The upper 8 bits are in
CONFIG15 register.The full 11 bit TX_QMC_GAINB(10:0) word is formatted as UNSIGNED with a range
or 0 to 1.9990.
Register Name – CONFIG15 – Address 0x114 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_GAINB(10:3)
TX_QMC_GAINB(10:3) – Upper 8 bits if the 11 bit QMC Gain word for DAC B.
Register Name – CONFIG16 – Address 0x115 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_PHASE(9:2)
TX_QMC_PHASE(9:2) – Upper Upper 8 bits if the 10 bit QMC Phase word. The lower two bits are in the
CONFIG17 register. The full QMC_PHASE(9:0) correction word is formatted as 2s complement and
scaled to occupy a range of -0.125 to 0.12475. To acomplish QMC Phase correction, this value is
multiplied by the current Q sample, then summed to the I sample.
Register Name – CONFIG17 – Address 0x116 Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
TX_QMC_PHASE(1:0) – Lower 2 bits of the 10 bit QMC Phase word .
<1>
<0>
TX_QMC_PHASE(1:0)
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REGISTER DESCRIPTIONS
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