TMS320WP010 Datasheet, PDF (14/18 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR FOR AEC/LEC/ANS

TMS320WP010
DIGITAL SIGNAL PROCESSOR
FOR AEC/LEC/ANS
SPRS040–OCTOBER 1995
SERIAL-PORT TRANSMIT, EXTERNAL CLOCKS, AND EXTERNAL FRAMES
switching characteristics over recommended operating conditions (see Note 3) (see Figure 11)
td(CXH-DXV)
tdis(CXH-DX)
th(CXH-DXV)
PARAMETER
Delay time, DX1 (DX2) valid after CLKX1 (CLKX2) high
Disable time, DX1 (DX2) invalid after CLKX1 (CLKX2) high
Hold time, DX1 (DX2) valid after CLKX1 (CLKX2) high
MIN MAX UNIT
25 ns
40† ns
–5
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t_c(CO)] (see Note 3) (see Figure 11)
MIN MAX UNIT
tc(SCK)
tf(SCK)
tr(SCK)
tw(SCK)
Cycle time, serial-port clock
Fall time, serial-port clock
Rise time, serial-port clock
Pulse duration, serial-port clock low/high
5.2H‡
2.1H‡
§ ns
6† ns
6† ns
ns
td(CXH-FXH) Delay time, FSX1 (FSX2) high after CLKX1 (CLKX2) high
2H – 8 ns
th(CXL-FXL) Hold time, FSX1 (FSX2) low after CLKX1 (CLKX2) low
7
ns
th(CXH-FXL) Hold time, FSX1 (FSX2) low after CLKX1 (CLKX2) high
2H – 8¶ ns
† _{Values derived from characterization data and not tested}
‡ _{Values ensured by design but not tested}
§ _{The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency}
of 0 Hz but tested at a much higher frequency to minimize test time.
¶ _{If the FSX1 (FSX2) pulse does not meet this specification, the first bit of serial data will be driven on the DX1 (DX2) pin until the falling edge of}
FSX1 (FSX2). After the falling edge of FSX1 (FSX2), data will be shifted out on the DX1 (DX2) pin. The transmit buffer empty interrupt will be
generated when the th(CXL-FXL) and th(CXH-FXL) specification is met.
NOTE 3: Internal clock with external FSX1 (FSX2) and vice versa are also allowable. However, FSX1 (FSX2) timings to CLKX1 (CLKX2) are
always defined depending on the source of FSX1 (FSX2), and CLKX1 (CLKX2) timings are always dependent upon the source of CLKX1
(CLKX2). Specifically, the relationship of FSX1 (FSX2) to CLKX1 (CLKX2) is independent of the source of CLKX1 (CLKX2).
CLKX1
(CLKX2)
FSX1
(FSX2)
DX1
(DX2)
BIt
tc(SCK)
tw(SCK)
tf(SCK)
td(CXH-FXH)
th(CXH-FXL)
th(CXL-FXL)
td(CXH-DXV)
tw(SCK)
tr(SCK)
th(CXH-DXV)
tdis(CXH-DX)
1
2
7/15
8/16
Figure 11. Serial-Port Transmit Timing of External Clocks and External Frames
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