OPT8320 Datasheet, PDF (12/88 Pages) Texas Instruments – OPT8320 3D Time-of-Flight Sensor

OPT8320
SBAS748 – DECEMBER 2015
www.ti.com
7.3.1.2 System Clock
The input clock to the system must be 24 MHz. By default, the TG functions at the same frequency as the input
frequency. Therefore, the system clock frequency (SYS_CLK_FREQ) is equal to the input frequency at the
MCLK pin.
7.3.1.3 Frame Rate Control and Sub-Frames
The OPT8320 supports master and slave modes of operation for the start of frame timing. The parameters
shown in Table 5 control the master and slave behavior.
PARAMETER
TG_EN
SLAVE_MODE
SYNC_MODE
FRAME_SYNC_DELAY
Table 5. Master and Slave Parameters
DEFAULT
0
0
0
1
DESCRIPTION
Start the timing generator and, thus, the full chipset operation.
0 = Disable the timing generator
1 = Enable the timing generator
Puts the timing controller in slave mode. The timing controller waits for an external
sync through the VD_IN pin for the start of frames. By default, the timing controller
is in master mode.
Puts the timing controller in SYNC_MODE. The timing controller synchronizes with
an external input through the VD_IN pin for the start of frames, but does not
depend on the input. If both SLAVE_MODE and SYNC_MODE are enabled,
SYNC_MODE takes higher priority. By default, this mode is disabled.
The programmable delay between the external VD_IN pulse and the internal start
of frame. The delay must be at least one cycle.
In slave mode or sync mode, a positive pulse on the VD_IN pin can be used for synchronization. The pulse must
be a minimum of two system clocks cycles wide in order to be recognized correctly, as shown in Figure 5. In
slave mode, if another pulse is received before the end of the previous frame, the pulse is ignored. In sync
mode, because a pulse can be received by the OPT8320 anytime within a frame, the frame during which the
pulse is received is aborted and therefore disruption of output data is possible, resulting in a loss of information.
Min 2 Cycles
VD_IN
System Clock
Frame Number
FRAME_SYNC_DELAY
X
Figure 5. VD_IN Timing Diagram
X+1
12
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