W681308DG Datasheet, PDF (49/64 Pages) Nuvotem Talema – W681308 USB Audio Controller from Nuvoton integrates fast 8051 Microcontroller Unit (MCU)

W681308
XXXX PRODUCT DESCRIPTION
15.
Nuvoton 2-Wire Serial Bus
15.1 Overview
Nuvoton 2-wire serial bus (W2S) is a simple bi-directional 2-wire bus for efficient inter-IC control. This design is for W2S
master use only, and governed by the MCU. The W2S is used to both read/write EEPROM and to control various device
included I2C interface. The W2S controller is equipped with 35 bytes FIFO performing formatting and de-formatting. The
MCU can simply fill up the FIFO contents which consists of target device ID, high/low address (depend on the device format);
for reading, just set read enable, for writing, keep writing data to FIFO then set write enable to launch transmission. The W2S
controller supports 3 types of page writing, 8, 16 and 32 bytes. The W2S controller is designed to support maximum of 32
bytes per page. The FIFO depth can support 3 header bytes (one device ID, two address) and 32 bytes data. It has various
bus speed configurations to support wide range of EEPROM bus speed.
16.
ICE Function By JTAG STD. IEEE 1149.1
16.1 Overview
The W681308 MCU on-chip debugger function follows the JTAG standard. It provides 8 sets of breakpoints. There is no
watchpoint. There are five JTAG-style scan chains within the 8051 and peripheral logic, which enable embedded ICE logic.
The 5 JTAG interface pins TCK (JTAG test clock input), TMS (JTAG test mode select), TDI (JTAG test data input), TDO
(JTAG test data output) and nTRST (JTAG TAG controller reset) are needed to enable the operation. The JTAG interface
pins are multiplexed with other function pins.
16.2 Scan Chains and JTAG Interface
There are five JTAG-style scan chains within the TB51 core and peripheral logic interface. These enable debugging
operation and configuration of Embedded-ICE logic. An external pull low signal on nTRST will reset TAP controller or MCU
power-on reset will trigger TAP controller reset once.
16.3 Pin Description
Table 11 JTAG Pin Description
Pin Name
Type
Function
TCK
TMS
TDI
TDO
nTRST
IN
IN
IN
OUT
IN
JTAG Test clock with internal pull-up.
JTAG Test-Mode Select with internal pull-up.
JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of TCK.
JTAG Test Data Output. Data is shifted out on TDO at the rising edge of TCK. TDO
output is a tri-state driver with internal weakly pull-low resister.
JTAG TAP controller reset input with internal pull-up.
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