SM89S16R1 Datasheet, PDF (22/28 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded

SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Starting and stopping the RTC:
RTCS ($A1H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RTCen
Stable
SEC.5
SEC.4
SEC.3
SEC.2
SEC.1
SEC.0
The RTC Function is enable by set the RTCS.7 (RTCen=1), then the ALE and /PSEN pins will switch to X32OUT
and X32IN that for RTC function used, the ALE and PSEN signal output will disable; the crystal frequency is 32.768
KHz. See figure 17.
SW 1
R
1
2
J1
1
1
2
32768H z C lock in
X32in(/P S E N )
J2
1
Y1
32768Hz
In C hip
RTCen
X 32 o u t(A LE )
Figure 17 The RTC Crystal connect diagram
The stable bit (RTCS.6) will set to 1 when the RTC module stable. The design is about 31.25 ms; suggest waiting 2
second to use the RTC function. This bit will clear when RTCen bit set again.
The SEC [5:0] will show the second counter (range from 00H to 3BH), and the MIN [5:0] will show the minute
counter (range from 00H to 3BH) of RTC function. This two register will clear when RTCen bit set.
Interrupt:
IE1 ($A9H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EADC
ERTC
ERTC: When set to ‘1’, enable the RTC interrupt. If you want to use the RTC interrupt function, must enable the EA
bit in IE.7 and enable the ERTC bit in IE1.2.
EADC: When set to ‘1’, enable the ADC interrupt. If you want to use the ADC interrupt function, must enable the EA
bit in IE.7 and enable the EADC bit in IE1.3
RTCC ($A2H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
INT_SEL1 INT_SEL0 MIN.5
MIN.4
MIN.3
MIN.2
MIN.1
MIN.0
Then select the interrupt distribution in INT_SEL [1:0] in RTCC [7:6].
The RTC can select each of 4 interrupt sources: 0.5 second, 1 second, 0.5 minute, and 1 minute. The interrupt vector
is 43H, it can wake-up CPU from POWER-DOWN mode.
IFR ($AAH)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADCIF
RTCIF
ADCIF: When interrupt occupy the ADC interrupt flag (IFR.3) will set, and the CPU will execute the interrupt
subroutine at the interrupt vector 4BH. The ADC Interrupt Flag must clear by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
22
SM89S16R1 V1.0 JANUARY 2005