SM8951B Datasheet, PDF (15/18 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller

SyncMOS Technologies International, Inc.
RET
RETI
AJMP
LJMP
SJMP
JMP
JZ
JNZ
CJNE
CJNZ
CJNZ
CJNZ
DJNZ
DJNZ
NOP
addr11
addr16
rel
@A+DPTR
rel
rel
A, direct,rel
A, #data,rel
Rn, #data,rel
@Ri, #data,rel
Rn,rel
direct,rel
Return from subroutine
Return from interrupt
Jump only at 2k bytes Address
Jump to max 64K bytes Address
Jump on at 256 bytes
Jump to A+ DPTR
Jump if A = 0
Jump if A ≠ 0
Jump if A ≠ < direct >
Jump if A ≠ < #data >
Jump if Rn ≠ < #data >
Jump if @Ri ≠ < #data >
Decrement and jump if Rn not zero
Decrement and jump if direct not zero
No Operation
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
1
2
1
2
2
2
3
2
2
2
1
2
2
2
2
2
3
2
3
2
3
2
3
2
2
2
3
2
1
1
Extension Function Description
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bits free-running counter that generate reset signal if the counter overflows.
The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing
software dead loop or runaway. The WDT function can help user software recover form abnormal software condition.
The WDT is different from Timer0, Timer1 of general 8051. To prevent a WDT reset can be done by software
periodically clearing the WDT counter.
The SM8951B WDT has selectable divider input for the time base source clock. To select the divider input, the
setting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bits counter
starts to count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when
overflows. The WDTE bit will be cleared to 0 automatically when SM8951B been reset, either hardware reset or
WDT reset.
To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bits
counter and let the counter re-start to count from the beginning.
Watch Dog Timer Registers- WDT Control Register
WDTC ($9F)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
WDTE
Unused
CLEAR
Unused
Unused
PS2
PS1
PS0
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer clear bit
If set the CLEAR bit, Watch Dog Timer will be re-start. then this bit will be clear automaticlly .
PS2~PS0: Clock sourer divider bit
PS [2:0]
Divider (OSC in) Time Period (ms) @40MHZ
000
8
13.1
001
16
26.21
010
32
52.42
011
64
104.8
100
128
209.71
101
256
419.43
110
512
838.86
111
1024
1677.72
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
15
06/2009