SM79164 Datasheet, PDF (11/25 Pages) SyncMOS Technologies,Inc – 8 - Bit Micro-controller with 64KB flash & 4KB RAM embedded

SyncMOS Technologies International. Inc.
SM79164
1.4 I/O Pin Configuration
The ports 1, 2 and 3 of standard 8051 have internal pull-up resistor, and port 0 has open-drain outputs. Each I/O pin can be
used independently as an input or an output. For I/O ports to be used as an input pin, the port bit latch must contain a ‘1’
which turns off the output driver FET. Then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can be
pulled low by an external source. The port 0 has open-drain outputs which means its pull-ups are not active during normal
port operation. Writing ‘1’ to the port 0 bit latch will causing bit floating so that it can be used as a high-impedance input.
The port 4 used as GPIO will has the same function as port 1, 2 and 3.
output
data
input
data
port 0
pin _{standard 8051}
2. Port 4 for PLCC or QFP package:
output
data
input
data
port 1, 2 and 3
standard 8051
pin
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is located
at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, $D8)
Read / Write:
Reset value:
bit-7
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
P4.3
R/W
1
P4.2
R/W
1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
3. Watch Dog Timer
P4.1
R/W
1
bit-0
P4.0
R/W
1
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is
useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the
WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened.
The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.
There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is inde-
pendent to the system frequency.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count
with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when
SM79164 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of
the 16-bit counter and let the counter re-start to count from the beginning.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/26
Ver 2.1 SM79164 08/2006