HV9606 Datasheet, PDF (7/9 Pages) Supertex, Inc – HV9606 Current-Mode PWM Controller with Supervisor

HV9606
Functional Description – Continued
Current Sense and Current Limit
Current sensing is accomplished by means of a resistor connected
in series with the source of the external power MOSFET. There
are two independent comparators monitoring the voltage drop
across this resistor. One provides absolute peak current limiting at
0.5V_REF and the other provides peak current feedback to the PWM
control loop.
Gate charge, capacitive loading and reverse recovery of output
rectifier reflected to the drain of the power MOSFET results in high
current spike at the positive leading edge of gate drive when the
MOSFET is turning on. This can result in false tripping of the
current limit comparator or incorrect operation of the control loop.
To prevent this condition an 85nSec leading edge current sense
blanking circuit is incorporated in the HV9606. This blanking
period is sufficient in most applications to achieve stable operation.
However, additional filtering of the MOSFET turn on current spike
may be added by connecting a resistor in series with the (CS)
current sense pin and a capacitor from the current sense pin to
SGND pin.
Error Amplifier
The error amplifier has a minimum gain bandwidth of 1MHz. The
inverting and non-inverting inputs are available respectively at FB
and NI pins and the amplifier output is available at the COMP pin.
Maximum application flexibility is provided to the designer by
having all terminals of the error amplifier available. The design of
the error amplifier prevents its output from saturating to the high
rail (V_DD) thus providing very fast slew recovery capability.
Soft Start Control Circuit
The soft start circuit provides a nominal constant current output of
10µA at the SS pin for charging a capacitor connected to this pin.
The instantaneous voltage on the SS pin determines the high limit
of the error amplifier, thus forcing the PWM to start at minimum
output duty cycle and slowly increase the duty cycle until stable
closed loop operation is achieved. The value of the capacitor
should be selected to achieve this stable closed loop operation
before the voltage on the SS pin exceeds 1.2V at maximum output
load on the DC/DC converter.
Soft start can only be initiated if the STATUS output of the
SUPERVISOR circuit is low. The SS pin is pulled low, discharging
the capacitor and engaging soft restart whenever the VX2 UVLO
detects a low gate drive voltage.
PWM Circuit
The current mode PWM circuit operates at one half the oscillator
frequency with a duty cycle guaranteed not to exceed 50%. Its
minimum pulse width (typically 130nSec) provides a wide dynamic
control range especially when operating at low frequencies.
For the dynamic control range required by a given application the
maximum operating frequency can be determined using the
following equations.
t_ON = ( V_IN(MAX) / V_IN(MIN) ) x ( P_OUT(MAX) / P_OUT(MIN)) x D_MIN
f_OSC = 2 f_PWM < 1 / t_ON
Where t_ON is the maximum gate drive output on time, V_IN(MAX) and
V_IN(MIN) are the maximum and minimum input voltage, P_OUT(MAX) and
P_OUT(MIN) are the maximum and minimum output power, D_MIN is the
worst case minimum gate drive output duty cycle (195nSec), f_PWM
is the maximum gate drive switching frequency and f_OSC is the
maximum oscillator frequency.
Supervisor Circuit
The designer may use this voltage monitor circuit for various
applications. The supervisor circuit controls the function of the soft
start circuit, which will be enabled when the STATUS output pin is
in a low state. The STATUS output pin is low when the voltage on
the SENSE pin is less than 0.85V_REF – 100mV.
The supervisory circuit can be used to monitor the output voltage
of the DC/DC converter. When used in this manner the STATUS
output pin may be used as a supply monitor and power on reset
(POR) for a micro controller whenever the supply voltage decays
to a programmed voltage level. Using it in this manner in a non-
isolated topology, where the output voltage is used for
bootstrapping V_DD, it will inhibit soft start as long as the output is
within programmed limits, thereby providing a rapid restart after a
short duration input voltage dropout. This allows the minimization
of both input and output capacitors for a given system hold up time
requirement. In an Isolated topology, sizing the V_DD capacitor for a
hold up time greater than the output hold up time requirement will
similarly permit the minimization of the input and output capacitors.
The supervisory circuit can also be used as a high accuracy low
input voltage detection and inhibit circuit by connecting the
STATUS pin to the SS pin. Since the status pin has a 10µA
internal pull up it will double the charging current of the soft start
capacitor, thus the soft start capacitor value needs to be doubled
for the same soft start time. The SENSE pin may be connected
through a resistor divider to any monitored voltage source (other
than the output of the HV9606 based DC/DC converter) or to a
logic output. When the voltage on the SENSE pin falls below
0.85V_REF – 100mV, the SS pin will be pulled low, thereby inhibiting
the gate drive output and shutting down the converter. The
oscillator will operate even though the GATE output is held low and
the SYNC I/O pin will maintain synchronization with other system
components or provide a clock signal to the system.
Shut Down / Inhibit Operation
The HV9606 may be shut down or inhibited depending on the
system requirements.
Pulling the STOP pin down to SGND will shut down the HV9606,
placing it in a zero power (leakage only) mode where even the
oscillator is halted. This pull down may be accomplished with a
discrete MOSFET, an optocoupler, or the open drain/collector
output of a logic gate with at least 20V breakdown rating. Using
this shut down method will cause the SYNC pin to be pulled low,
thus synchronization of other components connected to the SYNC
line will be lost.
Provided the input voltage remains above the programmed stop
threshold, inhibit of the PWM can be achieved by pulling the SS
pin low to SGND, thereby forcing the gate drive output to a
permanent low state and guaranteeing a soft restart when SS pin
pull down is released. The internal start up regulator will power the
HV9606 thus the oscillator will operate and the SYNC I/O pin will
maintain synchronization with other system components or provide
a clock signal to the system. This pull down could be
accomplished with a discrete MOSFET, an optocoupler, or the
open drain/collector output of a logic gate with at least a 5V
breakdown rating.
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4/15/2002-R.L2
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] FAX: [phone] www.supertex.com