TP2635_07 Datasheet, PDF (5/5 Pages) Supertex, Inc – P- Channel Enhancement-Mode Vertical DMOS FETs

8-Lead SOIC Package Outline (LG)
4.90 ± 0.10
8
6.00 ± 0.20
3.90 ± 0.10
Note 2
TP2635/TP2640
1
Top View
1.75 MAX
1.25 MIN
5° - 15°
(4 PLCS)
0.17 - 0.25
45°
0.25 - 0.50
Note 2
0.10 - 0.25
1.27BSC
0.31 - 0.51
Side View
0.40 - 1.27
0° - 8°
End View
Notes:
1. All dimensions in millimeters. Angles in degrees.
2. If the corner is not chamfered, then a Pin 1 identifier
must be located within the area indicated.
3-Lead TO-92 Package Outline (N3)
0.135 MIN
0.080 - 0.105 ₁
23
Bottom View
0.170 - 0.210
0.175 - 0.205
Seating Plane
123
0.125 - 0.165
0.500 MIN
0.014 - 0.022
0.014 - 0.022
0.095 - 0.105
0.045 - 0.055
Front View
Side View
Notes:
All dimensions are in millimeters; all angles in degrees.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-TP2635_TP2640
C032807
5