VN0109_13 Datasheet, PDF (1/5 Pages) Supertex, Inc – N-Channel Enhancement-Mode Vertical DMOS FET

Supertex inc.
VN0109
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
►► Free from secondary breakdown
►► Low power drive requirement
►► Ease of paralleling
►► Low C_ISS and fast switching speeds
►► Excellent thermal stability
►► Integral source-drain diode
►► High input impedance and high gain
Applications
►► Motor controls
►► Converters
►► Amplifiers
►► Switches
►► Power supply circuits
►► Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
General Description
This enhancement-mode (normally-off) transistor utilizes
a vertical DMOS structure and Supertex’s well-proven,
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
of bipolar transistors and the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Part Number
Package Option
VN0109N3-G
TO-92
VN0109N3-G P002
VN0109N3-G P003
VN0109N3-G P005 TO-92
VN0109N3-G P013
VN0109N3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Packing
1000/Bag
2000/Reel
Absolute Maximum Ratings
Product Summary
BV_DSS/BV_DGS
R_DS(ON)
(max)
90V
3.0Ω
Pin Configuration
SOURCE
DRAIN
I_DSS
(min)
2.0A
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BV_DSS
BV_DGS
±20V
Operating and storage temperature
-55^OC to +150^OC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
GATE
TO-92
Product Marking
SiVN _{YY = Year Sealed}
0 1 0 9 _{WW = Week Sealed}
YYWW
= “Green” Packaging
Typical Thermal Resistance
Package
TO-92
θ_ja
132^OC/W
Package may or may not include the following marks: Si or
TO-92
Doc.# DSFP-VN0109
C081913
Supertex inc.
www.supertex.com